diff --git a/embassy-rp/src/flash.rs b/embassy-rp/src/flash.rs
index f2137ebe..6ab05ff0 100644
--- a/embassy-rp/src/flash.rs
+++ b/embassy-rp/src/flash.rs
@@ -162,8 +162,6 @@ impl<'d, T: Instance, const FLASH_SIZE: usize> Flash<'d, T, FLASH_SIZE> {
     /// - interrupts must be disabled
     /// - DMA must not access flash memory
     unsafe fn in_ram(&mut self, operation: impl FnOnce()) -> Result<(), Error> {
-        let dma_status = &mut [false; crate::dma::CHANNEL_COUNT];
-
         // Make sure we're running on CORE0
         let core_id: u32 = unsafe { pac::SIO.cpuid().read() };
         if core_id != 0 {
@@ -174,25 +172,15 @@ impl<'d, T: Instance, const FLASH_SIZE: usize> Flash<'d, T, FLASH_SIZE> {
         crate::multicore::pause_core1();
 
         critical_section::with(|_| {
-            // Pause all DMA channels for the duration of the ram operation
-            for (number, status) in dma_status.iter_mut().enumerate() {
-                let ch = crate::pac::DMA.ch(number as _);
-                *status = ch.ctrl_trig().read().en();
-                if *status {
-                    ch.ctrl_trig().modify(|w| w.set_en(false));
-                }
+            // Wait for all DMA channels in flash to finish before ram operation
+            const SRAM_LOWER: u32 = 0x2000_0000;
+            for n in 0..crate::dma::CHANNEL_COUNT {
+                let ch = crate::pac::DMA.ch(n);
+                while ch.read_addr().read() < SRAM_LOWER && ch.ctrl_trig().read().busy() {}
             }
 
             // Run our flash operation in RAM
             operation();
-
-            // Re-enable previously enabled DMA channels
-            for (number, status) in dma_status.iter().enumerate() {
-                let ch = crate::pac::DMA.ch(number as _);
-                if *status {
-                    ch.ctrl_trig().modify(|w| w.set_en(true));
-                }
-            }
         });
 
         // Resume CORE1 execution