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stm32/rcc: fix u5 pll, add hsi48.

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This commit is contained in:
Dario Nieuwenhuis 2023-01-11 17:57:22 +01:00
parent 0feecd5cde
commit 041531c829
1 changed files with 22 additions and 8 deletions
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30
embassy-stm32/src/rcc/u5.rs
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@ -295,6 +295,7 @@ pub struct Config {
pub apb1_pre: APBPrescaler,
pub apb2_pre: APBPrescaler,
pub apb3_pre: APBPrescaler,
pub hsi48: bool,
}
impl Default for Config {
@ -305,6 +306,7 @@ impl Default for Config {
apb1_pre: Default::default(),
apb2_pre: Default::default(),
apb3_pre: Default::default(),
hsi48: false,
}
}
}
@ -320,7 +322,6 @@ pub(crate) unsafe fn init(config: Config) {
RCC.cr().write(|w| {
w.set_msipllen(false);
w.set_msison(true);
w.set_msison(true);
});
while !RCC.cr().read().msisrdy() {}
@ -340,9 +341,20 @@ pub(crate) unsafe fn init(config: Config) {
}
ClockSrc::PLL1R(src, m, n, div) => {
let freq = match src {
PllSrc::MSI(_) => MSIRange::default().into(),
PllSrc::HSE(hertz) => hertz.0,
PllSrc::HSI16 => HSI_FREQ.0,
PllSrc::MSI(_) => {
// TODO: enable MSI
MSIRange::default().into()
}
PllSrc::HSE(hertz) => {
// TODO: enable HSE
hertz.0
}
PllSrc::HSI16 => {
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
HSI_FREQ.0
}
};
// disable
@ -355,6 +367,7 @@ pub(crate) unsafe fn init(config: Config) {
RCC.pll1cfgr().write(|w| {
w.set_pllm(m.into());
w.set_pllsrc(src.into());
w.set_pllren(true);
});
RCC.pll1divr().modify(|w| {
@ -365,15 +378,16 @@ pub(crate) unsafe fn init(config: Config) {
// Enable PLL
RCC.cr().modify(|w| w.set_pllon(0, true));
while !RCC.cr().read().pllrdy(0) {}
RCC.pll1cfgr().modify(|w| w.set_pllren(true));
RCC.cr().write(|w| w.set_pllon(0, true));
while !RCC.cr().read().pllrdy(0) {}
pll_ck
}
};
if config.hsi48 {
RCC.cr().modify(|w| w.set_hsi48on(true));
while !RCC.cr().read().hsi48rdy() {}
}
// TODO make configurable
let power_vos = VoltageScale::Range4;