From 0421c57bd6b47214c87a58d7ad474f5c065af6e9 Mon Sep 17 00:00:00 2001
From: Thales Fragoso <thales.fragosoz@gmail.com>
Date: Thu, 29 Jul 2021 18:36:04 -0300
Subject: [PATCH] F4: Add PWR configuration to PLL

---
 embassy-stm32/src/pwr/mod.rs    |  1 +
 embassy-stm32/src/pwr/none.rs   |  1 +
 embassy-stm32/src/rcc/f4/mod.rs | 15 +++++++++++++--
 stm32-data                      |  2 +-
 4 files changed, 16 insertions(+), 3 deletions(-)
 create mode 100644 embassy-stm32/src/pwr/none.rs

diff --git a/embassy-stm32/src/pwr/mod.rs b/embassy-stm32/src/pwr/mod.rs
index 5b563d72..f0d47ca8 100644
--- a/embassy-stm32/src/pwr/mod.rs
+++ b/embassy-stm32/src/pwr/mod.rs
@@ -1,4 +1,5 @@
 #[cfg_attr(any(pwr_h7, pwr_h7smps), path = "h7.rs")]
+#[cfg_attr(not(any(pwr_h7, pwr_h7smps)), path = "none.rs")]
 mod _version;
 
 pub use _version::*;
diff --git a/embassy-stm32/src/pwr/none.rs b/embassy-stm32/src/pwr/none.rs
new file mode 100644
index 00000000..8b137891
--- /dev/null
+++ b/embassy-stm32/src/pwr/none.rs
@@ -0,0 +1 @@
+
diff --git a/embassy-stm32/src/rcc/f4/mod.rs b/embassy-stm32/src/rcc/f4/mod.rs
index 0962d252..1cf3e5bd 100644
--- a/embassy-stm32/src/rcc/f4/mod.rs
+++ b/embassy-stm32/src/rcc/f4/mod.rs
@@ -1,4 +1,4 @@
-use crate::pac::{FLASH, RCC};
+use crate::pac::{FLASH, PWR, RCC};
 use crate::peripherals;
 use crate::rcc::{get_freqs, set_freqs, Clocks};
 use crate::time::Hertz;
@@ -39,6 +39,7 @@ impl<'d> Rcc<'d> {
     }
 
     fn freeze(mut self) -> Clocks {
+        use super::sealed::RccPeripheral;
         use crate::pac::rcc::vals::{Hpre, Hsebyp, Ppre, Sw};
 
         let pllsrcclk = self.config.hse.map(|hse| hse.0).unwrap_or(HSI);
@@ -138,7 +139,17 @@ impl<'d> Rcc<'d> {
         if plls.use_pll {
             unsafe {
                 RCC.cr().modify(|w| w.set_pllon(true));
-                // TODO: PWR setup for HCLK > 168MHz
+
+                if hclk > 168_000_000 {
+                    peripherals::PWR::enable();
+
+                    PWR.cr().modify(|w| w.set_oden(true));
+                    while !PWR.csr().read().odrdy() {}
+
+                    PWR.cr().modify(|w| w.set_odswen(true));
+                    while !PWR.csr().read().odswrdy() {}
+                }
+
                 while !RCC.cr().read().pllrdy() {}
             }
         }
diff --git a/stm32-data b/stm32-data
index 62c89852..0ad27b2f 160000
--- a/stm32-data
+++ b/stm32-data
@@ -1 +1 @@
-Subproject commit 62c8985228186a02a623d1acfb59b75a4865d303
+Subproject commit 0ad27b2fd1126c6c9d9f4602d1331f5d82f4aa26