Checkpoint DMAMUX channel setup.
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@ -57,7 +57,7 @@ impl<'d, T: Instance> Uart<'d, T> {
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}
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}
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#[cfg(dma)]
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#[cfg(any(dma, dmamux))]
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pub async fn write_dma(&mut self, ch: &mut impl TxDma<T>, buffer: &[u8]) -> Result<(), Error> {
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unsafe {
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self.inner.regs().cr3().modify(|reg| {
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