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overhaul implementation

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This commit is contained in:
xoviat 2020-12-28 20:48:26 -06:00
parent 3cf85df176
commit 04944b6379
4 changed files with 250 additions and 640 deletions
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1
embassy-stm32f4/Cargo.toml
View File

@ -39,4 +39,5 @@ log = { version = "0.4.11", optional = true }
cortex-m-rt = "0.6.13"
cortex-m = { version = "0.6.4" }
embedded-hal = { version = "0.2.4" }
embedded-dma = { version = "0.1.2" }
stm32f4xx-hal = { version = "0.8.3", features = ["rt"], git = "https://github.com/stm32-rs/stm32f4xx-hal.git" }

129
embassy-stm32f4/src/interrupt.rs
View File

@ -1,129 +0,0 @@
//! Interrupt management
//!
//! This module implements an API for managing interrupts compatible with
//! nrf_softdevice::interrupt. Intended for switching between the two at compile-time.
use core::sync::atomic::{compiler_fence, Ordering};
use crate::pac::{NVIC, NVIC_PRIO_BITS};
// Re-exports
pub use crate::pac::Interrupt;
pub use crate::pac::Interrupt::*; // needed for cortex-m-rt #[interrupt]
pub use cortex_m::interrupt::{CriticalSection, Mutex};
#[derive(Debug, Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum Priority {
Level0 = 0,
Level1 = 1,
Level2 = 2,
Level3 = 3,
Level4 = 4,
Level5 = 5,
Level6 = 6,
Level7 = 7,
}
impl Priority {
#[inline]
fn to_nvic(self) -> u8 {
(self as u8) << (8 - NVIC_PRIO_BITS)
}
#[inline]
fn from_nvic(priority: u8) -> Self {
match priority >> (8 - NVIC_PRIO_BITS) {
0 => Self::Level0,
1 => Self::Level1,
2 => Self::Level2,
3 => Self::Level3,
4 => Self::Level4,
5 => Self::Level5,
6 => Self::Level6,
7 => Self::Level7,
_ => unreachable!(),
}
}
}
#[inline]
pub fn free<F, R>(f: F) -> R
where
F: FnOnce(&CriticalSection) -> R,
{
unsafe {
// TODO: assert that we're in privileged level
// Needed because disabling irqs in non-privileged level is a noop, which would break safety.
let primask: u32;
asm!("mrs {}, PRIMASK", out(reg) primask);
asm!("cpsid i");
// Prevent compiler from reordering operations inside/outside the critical section.
compiler_fence(Ordering::SeqCst);
let r = f(&CriticalSection::new());
compiler_fence(Ordering::SeqCst);
if primask & 1 == 0 {
asm!("cpsie i");
}
r
}
}
#[inline]
pub fn enable(irq: Interrupt) {
unsafe {
NVIC::unmask(irq);
}
}
#[inline]
pub fn disable(irq: Interrupt) {
NVIC::mask(irq);
}
#[inline]
pub fn is_active(irq: Interrupt) -> bool {
NVIC::is_active(irq)
}
#[inline]
pub fn is_enabled(irq: Interrupt) -> bool {
NVIC::is_enabled(irq)
}
#[inline]
pub fn is_pending(irq: Interrupt) -> bool {
NVIC::is_pending(irq)
}
#[inline]
pub fn pend(irq: Interrupt) {
NVIC::pend(irq)
}
#[inline]
pub fn unpend(irq: Interrupt) {
NVIC::unpend(irq)
}
#[inline]
pub fn get_priority(irq: Interrupt) -> Priority {
Priority::from_nvic(NVIC::get_priority(irq))
}
#[inline]
pub fn set_priority(irq: Interrupt, prio: Priority) {
unsafe {
cortex_m::peripheral::Peripherals::steal()
.NVIC
.set_priority(irq, prio.to_nvic())
}
}

2
embassy-stm32f4/src/lib.rs
View File

@ -331,6 +331,7 @@ pub use stm32f4xx_hal::stm32 as pac;
macro_rules! waker_interrupt {
($INT:ident, $waker:expr) => {{
use core::sync::atomic::{self, Ordering};
use core::task::Waker;
use stm32f4xx_hal::pac::{interrupt, Interrupt, NVIC};
static mut WAKER: Option<Waker> = None;
@ -359,7 +360,6 @@ macro_rules! waker_interrupt {
// This mod MUST go first, so that the others see its macros.
pub(crate) mod fmt;
pub mod interrupt;
pub mod uarte;
pub use cortex_m_rt::interrupt;

722
embassy-stm32f4/src/uarte.rs
View File

@ -1,11 +1,12 @@
//! HAL interface to the UARTE peripheral
//! Async low power UARTE.
//!
//! See product specification:
//!
//! - nrf52832: Section 35
//! - nrf52840: Section 6.34
//! The peripheral is autmatically enabled and disabled as required to save power.
//! Lowest power consumption can only be guaranteed if the send receive futures
//! are dropped correctly (e.g. not using `mem::forget()`).
use core::cell::UnsafeCell;
use core::cmp::min;
use core::future::Future;
use core::marker::PhantomPinned;
use core::ops::Deref;
use core::pin::Pin;
@ -14,10 +15,17 @@ use core::sync::atomic::{compiler_fence, Ordering};
use core::task::{Context, Poll};
use cortex_m::singleton;
use embassy::util::Signal;
use embedded_dma::{StaticReadBuffer, StaticWriteBuffer};
use crate::fmt::assert;
use crate::hal::dma::config::DmaConfig;
use crate::hal::dma::{Channel4, PeripheralToMemory, Stream2, StreamsTuple, Transfer};
use crate::hal::gpio::gpioa::{PA10, PA9};
use crate::hal::gpio::{Alternate, AF10, AF7, AF9};
use crate::hal::gpio::{Floating, Input, Output, PushPull};
use crate::hal::pac;
use crate::hal::prelude::*;
use crate::hal::rcc::Clocks;
use crate::hal::serial::config::{
Config as SerialConfig, DmaConfig as SerialDmaConfig, Parity, StopBits, WordLength,
@ -26,156 +34,51 @@ use crate::hal::serial::Serial;
use crate::hal::time::Bps;
use crate::interrupt;
use crate::interrupt::CriticalSection;
use crate::pac::Interrupt;
use crate::pac::{DMA2, USART1};
use embedded_hal::digital::v2::OutputPin;
// Re-export SVD variants to allow user to directly set values
// pub use uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Parity};
// Re-export SVD variants to allow user to directly set values.
// pub use pac::uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Parity};
use embassy::io::{AsyncBufRead, AsyncWrite, Result};
use embassy::util::WakerStore;
use crate::fmt::{assert, panic, todo, *};
//use crate::trace;
const RINGBUF_SIZE: usize = 512;
struct RingBuf {
buf: [u8; RINGBUF_SIZE],
start: usize,
end: usize,
empty: bool,
/// Interface to the UARTE peripheral
pub struct Uarte {
instance: Serial<USART1, (PA9<Alternate<AF7>>, PA10<Alternate<AF7>>)>,
usart: USART1,
dma: DMA2,
}
impl RingBuf {
fn new() -> Self {
RingBuf {
buf: [0; RINGBUF_SIZE],
start: 0,
end: 0,
empty: true,
}
struct State {
tx_done: Signal<()>,
rx_done: Signal<u32>,
}
fn push_buf(&mut self) -> &mut [u8] {
if self.start == self.end && !self.empty {
trace!(" ringbuf: push_buf empty");
return &mut self.buf[..0];
}
let n = if self.start <= self.end {
RINGBUF_SIZE - self.end
} else {
self.start - self.end
static STATE: State = State {
tx_done: Signal::new(),
rx_done: Signal::new(),
};
trace!(" ringbuf: push_buf {:?}..{:?}", self.end, self.end + n);
&mut self.buf[self.end..self.end + n]
pub struct Pins {
pub rxd: PA10<Alternate<AF7>>,
pub txd: PA9<Alternate<AF7>>,
pub dma: DMA2,
pub usart: USART1,
}
fn push(&mut self, n: usize) {
trace!(" ringbuf: push {:?}", n);
if n == 0 {
return;
}
impl Uarte {
pub fn new(mut pins: Pins, parity: Parity, baudrate: Bps, clocks: Clocks) -> Self {
// // Enable interrupts
// uarte.events_endtx.reset();
// uarte.events_endrx.reset();
// uarte
// .intenset
// .write(|w| w.endtx().set().txstopped().set().endrx().set().rxto().set());
// // TODO: Set interrupt priority?
// interrupt::unpend(interrupt::UARTE0_UART0);
// interrupt::enable(interrupt::UARTE0_UART0);
self.end = Self::wrap(self.end + n);
self.empty = false;
}
fn pop_buf(&mut self) -> &mut [u8] {
if self.empty {
trace!(" ringbuf: pop_buf empty");
return &mut self.buf[..0];
}
let n = if self.end <= self.start {
RINGBUF_SIZE - self.start
} else {
self.end - self.start
};
trace!(" ringbuf: pop_buf {:?}..{:?}", self.start, self.start + n);
&mut self.buf[self.start..self.start + n]
}
fn pop(&mut self, n: usize) {
trace!(" ringbuf: pop {:?}", n);
if n == 0 {
return;
}
self.start = Self::wrap(self.start + n);
self.empty = self.start == self.end;
}
fn wrap(n: usize) -> usize {
assert!(n <= RINGBUF_SIZE);
if n == RINGBUF_SIZE {
0
} else {
n
}
}
}
#[derive(Copy, Clone, Debug, PartialEq)]
enum RxState {
Idle,
Receiving,
ReceivingReady,
Stopping,
}
#[derive(Copy, Clone, Debug, PartialEq)]
enum TxState {
Idle,
Transmitting(usize),
}
/// Interface to a UARTE instance
///
/// This is a very basic interface that comes with the following limitations:
/// - The UARTE instances share the same address space with instances of UART.
/// You need to make sure that conflicting instances
/// are disabled before using `Uarte`. See product specification:
/// - nrf52832: Section 15.2
/// - nrf52840: Section 6.1.2
pub struct Uarte<T: Instance> {
started: bool,
state: UnsafeCell<UarteState<T>>,
}
// public because it needs to be used in Instance::{get_state, set_state}, but
// should not be used outside the module
#[doc(hidden)]
pub struct UarteState<T> {
inner: T,
rx: RingBuf,
rx_state: RxState,
rx_waker: WakerStore,
tx: RingBuf,
tx_state: TxState,
tx_waker: WakerStore,
_pin: PhantomPinned,
}
#[cfg(any(feature = "52833", feature = "52840"))]
fn port_bit(port: GpioPort) -> bool {
match port {
GpioPort::Port0 => false,
GpioPort::Port1 => true,
}
}
impl<T: Instance> Uarte<T> {
pub fn new(uarte: T, mut pins: Pins, parity: Parity, baudrate: Bps, clocks: Clocks) -> Self {
// Select pins
// Serial<USART1, (PA9<Alternate<AF7>>, PA10<Alternate<AF7>>)>
let mut serial = Serial::usart1(
pins.usart,
@ -191,411 +94,246 @@ impl<T: Instance> Uarte<T> {
)
.unwrap();
let isr = pins.dma.hisr;
// self.isr().$tcifX().bit_is_clear()
let isr = pins.dma.hisr;0
// Enable interrupts
// serial.listen(Event::Txe);
// serial.listen(Event::Txe);
Uarte { instance: serial, dma: pins.dma, usart: pins.usart }
}
// TODO: Enable idle interrupt? Use DMA interrupt?
// STREAM: Stream,
// CHANNEL: Channel,
// DIR: Direction,
// PERIPHERAL: PeriAddress,
// BUF: WriteBuffer<Word = <PERIPHERAL as PeriAddress>::MemSize> + 'static,
/// Sets the baudrate, parity and assigns the pins to the UARTE peripheral.
// TODO: Make it take the same `Pins` structs nrf-hal (with optional RTS/CTS).
// // TODO: #[cfg()] for smaller device variants without port register (nrf52810, ...).
// pub fn configure(
// &mut self,
// rxd: &Pin<Input<Floating>>,
// txd: &mut Pin<Output<PushPull>>,
// parity: Parity,
// baudrate: Baudrate,
// ) {
// let uarte = &self.instance;
// assert!(uarte.enable.read().enable().is_disabled());
//
// (Stream2<DMA2>, Channel4, Rx<pac::USART1>, PeripheralToMemory), //USART1_RX
// (Stream7<DMA2>, Channel4, Tx<pac::USART1>, MemoryToPeripheral), //USART1_TX
/*
Taken from https://gist.github.com/thalesfragoso/a07340c5df6eee3b04c42fdc69ecdcb1
*/
// let rcc = unsafe { &*RCC::ptr() };
// rcc.apb2enr.modify(|_, w| w.adc1en().enabled());
// rcc.apb2rstr.modify(|_, w| w.adcrst().set_bit());
// rcc.apb2rstr.modify(|_, w| w.adcrst().clear_bit());
// let adc = cx.device.ADC1;
// adc.cr2.modify(|_, w| {
// w.dma()
// .enabled()
// .cont()
// .continuous()
// .dds()
// .continuous()
// .adon()
// .enabled()
// uarte.psel.rxd.write(|w| {
// let w = unsafe { w.pin().bits(rxd.pin()) };
// let w = w.port().bit(rxd.port().bit());
// w.connect().connected()
// });
// Configure
//let hardware_flow_control = pins.rts.is_some() && pins.cts.is_some();
//uarte
// .config
// .write(|w| w.hwfc().bit(hardware_flow_control).parity().variant(parity));
// Configure frequency
//
// txd.set_high().unwrap();
// uarte.psel.txd.write(|w| {
// let w = unsafe { w.pin().bits(txd.pin()) };
// let w = w.port().bit(txd.port().bit());
// w.connect().connected()
// });
//
// uarte.baudrate.write(|w| w.baudrate().variant(baudrate));
// uarte.config.write(|w| w.parity().variant(parity));
// }
Uarte {
started: false,
state: UnsafeCell::new(UarteState {
inner: uarte,
// fn enable(&mut self) {
// self.instance.enable.write(|w| w.enable().enabled());
// }
rx: RingBuf::new(),
rx_state: RxState::Idle,
rx_waker: WakerStore::new(),
/// Sends serial data.
///
/// `tx_buffer` is marked as static as per `embedded-dma` requirements.
/// It it safe to use a buffer with a non static lifetime if memory is not
/// reused until the future has finished.
pub fn send<'a, B>(&'a mut self, tx_buffer: B) -> SendFuture<'a, B>
where
B: StaticReadBuffer<Word = u8>,
{
// Panic if TX is running which can happen if the user has called
// `mem::forget()` on a previous future after polling it once.
assert!(!self.tx_started());
tx: RingBuf::new(),
tx_state: TxState::Idle,
tx_waker: WakerStore::new(),
self.enable();
_pin: PhantomPinned,
}),
SendFuture {
uarte: self,
buf: tx_buffer,
}
}
fn with_state<'a, R>(
self: Pin<&'a mut Self>,
f: impl FnOnce(Pin<&'a mut UarteState<T>>) -> R,
) -> R {
let Self { state, started } = unsafe { self.get_unchecked_mut() };
interrupt::free(|cs| {
let ptr = state.get();
if !*started {
T::set_state(cs, ptr);
*started = true;
// safety: safe because critical section ensures only one *mut UartState
// exists at the same time.
unsafe { Pin::new_unchecked(&mut *ptr) }.start();
fn tx_started(&self) -> bool {
// self.instance.events_txstarted.read().bits() != 0
false
}
// safety: safe because critical section ensures only one *mut UartState
// exists at the same time.
f(unsafe { Pin::new_unchecked(&mut *ptr) })
})
/// Receives serial data.
///
/// The future is pending until the buffer is completely filled.
/// A common pattern is to use [`stop()`](ReceiveFuture::stop) to cancel
/// unfinished transfers after a timeout to prevent lockup when no more data
/// is incoming.
///
/// `rx_buffer` is marked as static as per `embedded-dma` requirements.
/// It it safe to use a buffer with a non static lifetime if memory is not
/// reused until the future has finished.
pub fn receive<'a, B>(&'a mut self, rx_buffer: B) -> ReceiveFuture<'a, B>
where
B: StaticWriteBuffer<Word = u8>,
{
// Panic if RX is running which can happen if the user has called
// `mem::forget()` on a previous future after polling it once.
assert!(!self.rx_started());
self.enable();
ReceiveFuture {
uarte: self,
buf: Some(rx_buffer),
}
}
impl<T: Instance> Drop for Uarte<T> {
fn drop(&mut self) {
// stop DMA before dropping, because DMA is using the buffer in `self`.
todo!()
fn rx_started(&self) -> bool {
self.instance.events_rxstarted.read().bits() != 0
}
}
impl<T: Instance> AsyncBufRead for Uarte<T> {
fn poll_fill_buf(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Result<&[u8]>> {
self.with_state(|s| s.poll_fill_buf(cx))
/// Future for the [`LowPowerUarte::send()`] method.
pub struct SendFuture<'a, B> {
uarte: &'a Uarte,
buf: B,
}
fn consume(self: Pin<&mut Self>, amt: usize) {
self.with_state(|s| s.consume(amt))
impl<'a, B> Drop for SendFuture<'a, B> {
fn drop(self: &mut Self) {
if self.uarte.tx_started() {
trace!("stoptx");
// Stop the transmitter to minimize the current consumption.
self.uarte
.instance
.tasks_stoptx
.write(|w| unsafe { w.bits(1) });
self.uarte.instance.events_txstarted.reset();
}
}
}
impl<T: Instance> AsyncWrite for Uarte<T> {
fn poll_write(self: Pin<&mut Self>, cx: &mut Context<'_>, buf: &[u8]) -> Poll<Result<usize>> {
self.with_state(|s| s.poll_write(cx, buf))
}
}
impl<'a, B> Future for SendFuture<'a, B>
where
B: StaticReadBuffer<Word = u8>,
{
type Output = ();
impl<T: Instance> UarteState<T> {
pub fn start(self: Pin<&mut Self>) {
interrupt::set_priority(T::interrupt(), interrupt::Priority::Level7);
interrupt::enable(T::interrupt());
interrupt::pend(T::interrupt());
}
fn poll(self: core::pin::Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<()> {
if self.is_ready() {
Poll::Ready(())
} else {
// Start DMA transaction
let uarte = &self.uarte.instance;
fn poll_fill_buf(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Result<&[u8]>> {
let this = unsafe { self.get_unchecked_mut() };
STATE.tx_done.reset();
let (ptr, len) = unsafe { self.buf.read_buffer() };
// assert!(len <= EASY_DMA_SIZE);
// TODO: panic if buffer is not in SRAM
// Conservative compiler fence to prevent optimizations that do not
// take in to account actions by DMA. The fence has been placed here,
// before any DMA action has started
compiler_fence(Ordering::SeqCst);
trace!("poll_read");
// uarte.txd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
// uarte
// .txd
// .maxcnt
// .write(|w| unsafe { w.maxcnt().bits(len as _) });
// We have data ready in buffer? Return it.
let buf = this.rx.pop_buf();
if buf.len() != 0 {
trace!(" got {:?} {:?}", buf.as_ptr() as u32, buf.len());
return Poll::Ready(Ok(buf));
}
trace!(" empty");
if this.rx_state == RxState::ReceivingReady {
trace!(" stopping");
this.rx_state = RxState::Stopping;
this.inner.tasks_stoprx.write(|w| unsafe { w.bits(1) });
}
this.rx_waker.store(cx.waker());
Poll::Pending
}
fn consume(self: Pin<&mut Self>, amt: usize) {
let this = unsafe { self.get_unchecked_mut() };
trace!("consume {:?}", amt);
this.rx.pop(amt);
interrupt::pend(T::interrupt());
}
fn poll_write(self: Pin<&mut Self>, cx: &mut Context<'_>, buf: &[u8]) -> Poll<Result<usize>> {
let this = unsafe { self.get_unchecked_mut() };
trace!("poll_write: {:?}", buf.len());
let tx_buf = this.tx.push_buf();
if tx_buf.len() == 0 {
trace!("poll_write: pending");
this.tx_waker.store(cx.waker());
return Poll::Pending;
}
let n = min(tx_buf.len(), buf.len());
tx_buf[..n].copy_from_slice(&buf[..n]);
this.tx.push(n);
trace!("poll_write: queued {:?}", n);
// Conservative compiler fence to prevent optimizations that do not
// take in to account actions by DMA. The fence has been placed here,
// before any DMA action has started
compiler_fence(Ordering::SeqCst);
interrupt::pend(T::interrupt());
Poll::Ready(Ok(n))
}
fn on_interrupt(&mut self) {
trace!("irq: start");
let mut more_work = true;
while more_work {
more_work = false;
match self.rx_state {
RxState::Idle => {
trace!(" irq_rx: in state idle");
if self.inner.events_rxdrdy.read().bits() != 0 {
trace!(" irq_rx: rxdrdy?????");
self.inner.events_rxdrdy.reset();
}
if self.inner.events_endrx.read().bits() != 0 {
panic!("unexpected endrx");
}
let buf = self.rx.push_buf();
if buf.len() != 0 {
trace!(" irq_rx: starting {:?}", buf.len());
self.rx_state = RxState::Receiving;
// Set up the DMA read
self.inner.rxd.ptr.write(|w|
// The PTR field is a full 32 bits wide and accepts the full range
// of values.
unsafe { w.ptr().bits(buf.as_ptr() as u32) });
self.inner.rxd.maxcnt.write(|w|
// We're giving it the length of the buffer, so no danger of
// accessing invalid memory. We have verified that the length of the
// buffer fits in an `u8`, so the cast to `u8` is also fine.
//
// The MAXCNT field is at least 8 bits wide and accepts the full
// range of values.
unsafe { w.maxcnt().bits(buf.len() as _) });
trace!(" irq_rx: buf {:?} {:?}", buf.as_ptr() as u32, buf.len());
// Enable RXRDY interrupt.
self.inner.events_rxdrdy.reset();
self.inner.intenset.write(|w| w.rxdrdy().set());
// Start UARTE Receive transaction
self.inner.tasks_startrx.write(|w|
// `1` is a valid value to write to task registers.
unsafe { w.bits(1) });
}
}
RxState::Receiving => {
trace!(" irq_rx: in state receiving");
if self.inner.events_rxdrdy.read().bits() != 0 {
trace!(" irq_rx: rxdrdy");
// Disable the RXRDY event interrupt
// RXRDY is triggered for every byte, but we only care about whether we have
// some bytes or not. So as soon as we have at least one, disable it, to avoid
// wasting CPU cycles in interrupts.
self.inner.intenclr.write(|w| w.rxdrdy().clear());
self.inner.events_rxdrdy.reset();
self.rx_waker.wake();
self.rx_state = RxState::ReceivingReady;
more_work = true; // in case we also have endrx pending
}
}
RxState::ReceivingReady | RxState::Stopping => {
trace!(" irq_rx: in state ReceivingReady");
if self.inner.events_rxdrdy.read().bits() != 0 {
trace!(" irq_rx: rxdrdy");
self.inner.events_rxdrdy.reset();
}
if self.inner.events_endrx.read().bits() != 0 {
let n: usize = self.inner.rxd.amount.read().amount().bits() as usize;
trace!(" irq_rx: endrx {:?}", n);
self.rx.push(n);
self.inner.events_endrx.reset();
self.rx_waker.wake();
self.rx_state = RxState::Idle;
more_work = true; // start another rx if possible
}
}
}
}
more_work = true;
while more_work {
more_work = false;
match self.tx_state {
TxState::Idle => {
trace!(" irq_tx: in state Idle");
let buf = self.tx.pop_buf();
if buf.len() != 0 {
trace!(" irq_tx: starting {:?}", buf.len());
self.tx_state = TxState::Transmitting(buf.len());
// Set up the DMA write
self.inner.txd.ptr.write(|w|
// The PTR field is a full 32 bits wide and accepts the full range
// of values.
unsafe { w.ptr().bits(buf.as_ptr() as u32) });
self.inner.txd.maxcnt.write(|w|
// We're giving it the length of the buffer, so no danger of
// accessing invalid memory. We have verified that the length of the
// buffer fits in an `u8`, so the cast to `u8` is also fine.
//
// The MAXCNT field is 8 bits wide and accepts the full range of
// values.
unsafe { w.maxcnt().bits(buf.len() as _) });
// Start UARTE Transmit transaction
self.inner.tasks_starttx.write(|w|
// `1` is a valid value to write to task registers.
unsafe { w.bits(1) });
}
}
TxState::Transmitting(n) => {
trace!(" irq_tx: in state Transmitting");
// Start the DMA transfer
// See https://github.com/mwkroening/async-stm32f1xx/blob/78c46d1bff124eae4ebc7a2f4d40e6ed74def8b5/src/serial.rs#L118-L129
// https://github.com/stm32-rs/stm32f1xx-hal/blob/68fd3d6f282173816fd3181e795988d314cb17d0/src/serial.rs#L649-L671
let first_buffer = singleton!(: [u8; 128] = [0; 128]).unwrap();
let second_buffer = singleton!(: [u8; 128] = [0; 128]).unwrap();
let triple_buffer = Some(singleton!(: [u8; 128] = [0; 128]).unwrap());
// let first_buffer = singleton!(: [u8; 128] = [0; 128]).unwrap();
// let second_buffer = singleton!(: [u8; 128] = [0; 128]).unwrap();
// let triple_buffer = Some(singleton!(: [u8; 128] = [0; 128]).unwrap());
let transfer = Transfer::init(
StreamsTuple::new(pins.dma).7,
pins.usart,
first_buffer,
Some(second_buffer),
StreamsTuple::new(self.dma).2,
self.usart,
self.buf,
// Some(second_buffer),
None,
DmaConfig::default()
.transfer_complete_interrupt(true)
.memory_increment(true)
.double_buffer(true),
.double_buffer(false),
);
if self.inner.events_endtx.read().bits() != 0 {
self.inner.events_endtx.reset();
trace!(" irq_tx: endtx {:?}", n);
self.tx.pop(n);
self.tx_waker.wake();
self.tx_state = TxState::Idle;
more_work = true; // start another tx if possible
waker_interrupt!(DMA2_STREAM2, cx.waker().clone());
Poll::Pending
}
}
}
}
trace!("irq: end");
}
}
pub struct Pins {
pub rxd: PA10<Alternate<AF7>>,
pub txd: PA9<Alternate<AF7>>,
pub dma: DMA2,
pub usart: USART1,
// pub cts: Option<GpioPin<Input<Floating>>>,
// pub rts: Option<GpioPin<Output<PushPull>>>,
/// Future for the [`Uarte::receive()`] method.
pub struct ReceiveFuture<'a, B> {
uarte: &'a Uarte,
buf: Option<B>,
}
mod private {
pub trait Sealed {}
impl<'a, B> Drop for ReceiveFuture<'a, B> {
fn drop(self: &mut Self) {
if self.uarte.rx_started() {
trace!("stoprx");
impl Sealed for crate::pac::UARTE0 {}
#[cfg(any(feature = "52833", feature = "52840", feature = "9160"))]
impl Sealed for crate::pac::UARTE1 {}
self.uarte
.instance
.tasks_stoprx
.write(|w| unsafe { w.bits(1) });
self.uarte.instance.events_rxstarted.reset();
}
pub trait Instance: Deref<Target = uarte0::RegisterBlock> + Sized + private::Sealed {
fn interrupt() -> Interrupt;
#[doc(hidden)]
fn get_state(_cs: &CriticalSection) -> *mut UarteState<Self>;
#[doc(hidden)]
fn set_state(_cs: &CriticalSection, state: *mut UarteState<Self>);
}
#[interrupt]
unsafe fn DMA2_CHANNEL2() {
interrupt::free(|cs| UARTE0::get_state(cs).as_mut().unwrap().on_interrupt());
}
#[interrupt]
unsafe fn DMA2_CHANNEL7() {
interrupt::free(|cs| UARTE1::get_state(cs).as_mut().unwrap().on_interrupt());
}
static mut UARTE0_STATE: *mut UarteState<UARTE0> = ptr::null_mut();
#[cfg(any(feature = "52833", feature = "52840", feature = "9160"))]
static mut UARTE1_STATE: *mut UarteState<UARTE1> = ptr::null_mut();
impl Instance for DMA_CHANNEL1 {
fn interrupt() -> Interrupt {
Interrupt::UARTE0_UART0
}
fn get_state(_cs: &CriticalSection) -> *mut UarteState<Self> {
unsafe { UARTE0_STATE } // Safe because of CriticalSection
}
fn set_state(_cs: &CriticalSection, state: *mut UarteState<Self>) {
unsafe { UARTE0_STATE = state } // Safe because of CriticalSection
}
}
#[cfg(any(feature = "52833", feature = "52840", feature = "9160"))]
impl Instance for UARTE1 {
fn interrupt() -> Interrupt {
Interrupt::UARTE1
impl<'a, B> Future for ReceiveFuture<'a, B>
where
B: StaticWriteBuffer<Word = u8>,
{
type Output = B;
fn poll(self: core::pin::Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<B> {
if self.is_ready() {
Poll::Ready(())
} else {
// Start DMA transaction
compiler_fence(Ordering::SeqCst);
// uarte.txd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
// uarte
// .txd
// .maxcnt
// .write(|w| unsafe { w.maxcnt().bits(len as _) });
// Start the DMA transfer
// See https://github.com/mwkroening/async-stm32f1xx/blob/78c46d1bff124eae4ebc7a2f4d40e6ed74def8b5/src/serial.rs#L118-L129
// https://github.com/stm32-rs/stm32f1xx-hal/blob/68fd3d6f282173816fd3181e795988d314cb17d0/src/serial.rs#L649-L671
// let first_buffer = singleton!(: [u8; 128] = [0; 128]).unwrap();
// let second_buffer = singleton!(: [u8; 128] = [0; 128]).unwrap();
// let triple_buffer = Some(singleton!(: [u8; 128] = [0; 128]).unwrap());
let transfer = Transfer::init(
StreamsTuple::new(self.dma).7,
self.usart,
self.buf,
// Some(second_buffer),
None,
DmaConfig::default()
.transfer_complete_interrupt(true)
.memory_increment(true)
.double_buffer(false),
);
waker_interrupt!(DMA2_STREAM7, cx.waker().clone());
Poll::Pending
}
}
}
fn get_state(_cs: &CriticalSection) -> *mut UarteState<Self> {
unsafe { UARTE1_STATE } // Safe because of CriticalSection
}
fn set_state(_cs: &CriticalSection, state: *mut UarteState<Self>) {
unsafe { UARTE1_STATE = state } // Safe because of CriticalSection
/// Future for the [`receive()`] method.
impl<'a, B> ReceiveFuture<'a, B> {
/// Stops the ongoing reception and returns the number of bytes received.
pub async fn stop(mut self) -> (B, usize) {
let buf = self.buf.take().unwrap();
drop(self);
let len = STATE.rx_done.wait().await;
(buf, len as _)
}
}