Fix some typos

This commit is contained in:
Dirk Stolle
2023-05-08 23:25:01 +02:00
parent d0703f83db
commit 0584312ef0
28 changed files with 41 additions and 41 deletions

View File

@ -25,7 +25,7 @@ pub const ERASE_SIZE: usize = 4096;
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Error {
/// Opration using a location not in flash.
/// Operation using a location not in flash.
OutOfBounds,
/// Unaligned operation or using unaligned buffers.
Unaligned,

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@ -551,7 +551,7 @@ impl<'d, T: Instance + 'd, M: Mode> I2c<'d, T, M> {
if abort_reason.is_err() || (send_stop && last) {
// If the transaction was aborted or if it completed
// successfully wait until the STOP condition has occured.
// successfully wait until the STOP condition has occurred.
while !p.ic_raw_intr_stat().read().stop_det() {}

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@ -544,7 +544,7 @@ pub(crate) unsafe fn on_interrupt<T: Instance>(_: *mut ()) {
s.rx_waker.wake();
}
// Disable any further RX interrupts when the buffer becomes full or
// errors have occured. this lets us buffer additional errors in the
// errors have occurred. This lets us buffer additional errors in the
// fifo without needing more error storage locations, and most applications
// will want to do a full reset of their uart state anyway once an error
// has happened.

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@ -231,7 +231,7 @@ impl<'d, T: Instance> UartTx<'d, T, Async> {
}
impl<'d, T: Instance, M: Mode> UartRx<'d, T, M> {
/// Create a new DMA-enabled UART which can only recieve data
/// Create a new DMA-enabled UART which can only receive data
pub fn new(
_uart: impl Peripheral<P = T> + 'd,
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
@ -690,7 +690,7 @@ impl<'d, T: Instance, M: Mode> Uart<'d, T, M> {
self.tx.send_break(bits).await
}
/// Split the Uart into a transmitter and receiver, which is particuarly
/// Split the Uart into a transmitter and receiver, which is particularly
/// useful when having two tasks correlating to transmitting and receiving.
pub fn split(self) -> (UartTx<'d, T, M>, UartRx<'d, T, M>) {
(self.tx, self.rx)