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stm32/spi: do not clear rxfifo in SPIv3, the hw already does it.

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This commit is contained in:
Dario Nieuwenhuis 2022-03-15 02:37:08 +01:00
parent 4579192832
commit 059b164234
1 changed files with 7 additions and 2 deletions
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9
embassy-stm32/src/spi/mod.rs
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@ -462,6 +462,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
set_rxdmaen(T::REGS, true); set_rxdmaen(T::REGS, true);
} }
// SPIv3 clears rxfifo on SPE=0
#[cfg(not(spi_v3))]
flush_rx_fifo(T::REGS);
let clock_byte_count = data.len(); let clock_byte_count = data.len();
let rx_request = self.rxdma.request(); let rx_request = self.rxdma.request();
@ -522,8 +526,8 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
set_rxdmaen(T::REGS, true); set_rxdmaen(T::REGS, true);
} }
// TODO: This is unnecessary in some versions because // SPIv3 clears rxfifo on SPE=0
// clearing SPE automatically clears the fifos #[cfg(not(spi_v3))]
flush_rx_fifo(T::REGS); flush_rx_fifo(T::REGS);
let rx_request = self.rxdma.request(); let rx_request = self.rxdma.request();
@ -723,6 +727,7 @@ fn spin_until_rx_ready(regs: Regs) -> Result<(), Error> {
} }
} }
#[cfg(not(spi_v3))]
fn flush_rx_fifo(regs: Regs) { fn flush_rx_fifo(regs: Regs) {
unsafe { unsafe {
#[cfg(not(spi_v3))] #[cfg(not(spi_v3))]