stm32/rcc: unify l0l1 and l4l5.
This commit is contained in:
Dario Nieuwenhuis
parent
4fe344ebc0
commit
066dc297ed
@ -58,7 +58,7 @@ rand_core = "0.6.3"
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sdio-host = "0.5.0"
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embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
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critical-section = "1.1"
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-1374ed622714ef4702826699ca21cc1f741f4133" }
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-c551c07bf12513dd8346a9fe0bc70cf79f2ea02f" }
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vcell = "0.1.3"
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bxcan = "0.7.0"
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nb = "1.0.0"
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@ -76,7 +76,7 @@ critical-section = { version = "1.1", features = ["std"] }
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[build-dependencies]
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proc-macro2 = "1.0.36"
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quote = "1.0.15"
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-1374ed622714ef4702826699ca21cc1f741f4133", default-features = false, features = ["metadata"]}
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-c551c07bf12513dd8346a9fe0bc70cf79f2ea02f", default-features = false, features = ["metadata"]}
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[features]
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@ -1,12 +1,13 @@
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#[cfg(any(stm32l0, stm32l1))]
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pub use crate::pac::pwr::vals::Vos as VoltageScale;
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use crate::pac::rcc::regs::Cfgr;
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#[cfg(any(stm32l4, stm32l5, stm32wb))]
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#[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
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pub use crate::pac::rcc::vals::Adcsel as AdcClockSource;
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#[cfg(any(rcc_l0_v2, stm32l4, stm32l5, stm32wb))]
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pub use crate::pac::rcc::vals::Clk48sel as Clk48Src;
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#[cfg(any(stm32wb, stm32wl))]
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pub use crate::pac::rcc::vals::Hsepre as HsePrescaler;
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pub use crate::pac::rcc::vals::{
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Adcsel as AdcClockSource, Hpre as AHBPrescaler, Msirange as MSIRange, Pllm as PllPreDiv, Plln as PllMul,
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Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc as PllSource, Ppre as APBPrescaler, Sw as ClockSrc,
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};
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pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Msirange as MSIRange, Ppre as APBPrescaler, Sw as ClockSrc};
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use crate::pac::{FLASH, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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@ -33,25 +34,6 @@ pub struct Hse {
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pub prescaler: HsePrescaler,
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}
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#[derive(Clone, Copy)]
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pub struct Pll {
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/// PLL source
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pub source: PllSource,
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/// PLL pre-divider (DIVM).
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pub prediv: PllPreDiv,
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/// PLL multiplication factor.
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pub mul: PllMul,
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/// PLL P division factor. If None, PLL P output is disabled.
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pub divp: Option<PllPDiv>,
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/// PLL Q division factor. If None, PLL Q output is disabled.
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pub divq: Option<PllQDiv>,
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/// PLL R division factor. If None, PLL R output is disabled.
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pub divr: Option<PllRDiv>,
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}
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/// Clocks configuration
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pub struct Config {
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// base clock sources
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@ -79,13 +61,17 @@ pub struct Config {
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pub shared_ahb_pre: AHBPrescaler,
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// muxes
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#[cfg(any(stm32l4, stm32l5, stm32wb))]
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#[cfg(any(rcc_l0_v2, stm32l4, stm32l5, stm32wb))]
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pub clk48_src: Clk48Src,
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// low speed LSI/LSE/RTC
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pub ls: super::LsConfig,
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#[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
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pub adc_clock_source: AdcClockSource,
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#[cfg(any(stm32l0, stm32l1))]
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pub voltage_scale: VoltageScale,
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}
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impl Default for Config {
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@ -110,10 +96,13 @@ impl Default for Config {
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pllsai2: None,
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#[cfg(crs)]
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hsi48: Some(Default::default()),
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#[cfg(any(stm32l4, stm32l5, stm32wb))]
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#[cfg(any(rcc_l0_v2, stm32l4, stm32l5, stm32wb))]
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clk48_src: Clk48Src::HSI48,
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ls: Default::default(),
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#[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
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adc_clock_source: AdcClockSource::SYS,
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#[cfg(any(stm32l0, stm32l1))]
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voltage_scale: VoltageScale::RANGE1,
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}
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}
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}
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@ -152,20 +141,26 @@ pub const WPAN_DEFAULT: Config = Config {
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adc_clock_source: AdcClockSource::SYS,
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};
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fn msi_enable(range: MSIRange) {
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#[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
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RCC.cr().modify(|w| {
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#[cfg(not(stm32wb))]
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w.set_msirgsel(crate::pac::rcc::vals::Msirgsel::CR);
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w.set_msirange(range);
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w.set_msipllen(false);
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});
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#[cfg(any(stm32l0, stm32l1))]
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RCC.icscr().modify(|w| w.set_msirange(range));
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RCC.cr().modify(|w| w.set_msion(true));
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while !RCC.cr().read().msirdy() {}
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}
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pub(crate) unsafe fn init(config: Config) {
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// Switch to MSI to prevent problems with PLL configuration.
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if !RCC.cr().read().msion() {
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// Turn on MSI and configure it to 4MHz.
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RCC.cr().modify(|w| {
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#[cfg(not(stm32wb))]
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w.set_msirgsel(crate::pac::rcc::vals::Msirgsel::CR);
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w.set_msirange(MSIRange::RANGE4M);
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w.set_msipllen(false);
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w.set_msion(true)
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});
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// Wait until MSI is running
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while !RCC.cr().read().msirdy() {}
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msi_enable(MSIRange::RANGE4M)
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}
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if RCC.cfgr().read().sws() != ClockSrc::MSI {
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// Set MSI as a clock source, reset prescalers.
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@ -174,6 +169,14 @@ pub(crate) unsafe fn init(config: Config) {
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while RCC.cfgr().read().sws() != ClockSrc::MSI {}
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}
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// Set voltage scale
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#[cfg(any(stm32l0, stm32l1))]
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{
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while crate::pac::PWR.csr().read().vosf() {}
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crate::pac::PWR.cr().write(|w| w.set_vos(config.voltage_scale));
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while crate::pac::PWR.csr().read().vosf() {}
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}
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#[cfg(stm32l5)]
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crate::pac::PWR.cr1().modify(|w| {
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w.set_vos(crate::pac::pwr::vals::Vos::RANGE0);
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@ -182,21 +185,16 @@ pub(crate) unsafe fn init(config: Config) {
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let rtc = config.ls.init();
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let msi = config.msi.map(|range| {
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// Enable MSI
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RCC.cr().modify(|w| {
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#[cfg(not(stm32wb))]
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w.set_msirgsel(crate::pac::rcc::vals::Msirgsel::CR);
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w.set_msirange(range);
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w.set_msion(true);
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// If LSE is enabled, enable calibration of MSI
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w.set_msipllen(config.ls.lse.is_some());
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});
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while !RCC.cr().read().msirdy() {}
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msi_enable(range);
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msirange_to_hertz(range)
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});
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// If LSE is enabled and the right freq, enable calibration of MSI
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#[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
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if config.ls.lse.map(|x| x.frequency) == Some(Hertz(32_768)) {
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RCC.cr().modify(|w| w.set_msipllen(true));
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}
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let hsi = config.hsi.then(|| {
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RCC.cr().modify(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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@ -218,7 +216,10 @@ pub(crate) unsafe fn init(config: Config) {
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});
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#[cfg(crs)]
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let _hsi48 = config.hsi48.map(super::init_hsi48);
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let _hsi48 = config.hsi48.map(|config| {
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//
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super::init_hsi48(config)
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});
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#[cfg(not(crs))]
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let _hsi48: Option<Hertz> = None;
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@ -251,7 +252,12 @@ pub(crate) unsafe fn init(config: Config) {
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}),
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};
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let pll_input = PllInput { hse, hsi, msi };
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let pll_input = PllInput {
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hse,
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hsi,
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#[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
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msi,
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};
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let pll = init_pll(PllInstance::Pll, config.pll, &pll_input);
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#[cfg(any(stm32l4, stm32l5, stm32wb))]
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let pllsai1 = init_pll(PllInstance::Pllsai1, config.pllsai1, &pll_input);
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@ -265,10 +271,13 @@ pub(crate) unsafe fn init(config: Config) {
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ClockSrc::PLL1_R => pll.r.unwrap(),
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};
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#[cfg(stm32l4)]
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#[cfg(any(rcc_l0_v2, stm32l4, stm32l5, stm32wb))]
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RCC.ccipr().modify(|w| w.set_clk48sel(config.clk48_src));
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#[cfg(stm32l5)]
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RCC.ccipr1().modify(|w| w.set_clk48sel(config.clk48_src));
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#[cfg(any(rcc_l0_v2))]
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let _clk48 = match config.clk48_src {
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Clk48Src::HSI48 => _hsi48,
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Clk48Src::PLL1_VCO_DIV_2 => pll.clk48,
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};
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#[cfg(any(stm32l4, stm32l5, stm32wb))]
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let _clk48 = match config.clk48_src {
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Clk48Src::HSI48 => _hsi48,
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@ -285,16 +294,23 @@ pub(crate) unsafe fn init(config: Config) {
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let hclk1 = sys_clk / config.ahb_pre;
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let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk1, config.apb1_pre);
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let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk1, config.apb2_pre);
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#[cfg(not(any(stm32wl5x, stm32wb)))]
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#[cfg(any(stm32l4, stm32l5, stm32wlex))]
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let hclk2 = hclk1;
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#[cfg(any(stm32wl5x, stm32wb))]
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let hclk2 = sys_clk / config.core2_ahb_pre;
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#[cfg(not(any(stm32wl, stm32wb)))]
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#[cfg(any(stm32l4, stm32l5, stm32wlex))]
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let hclk3 = hclk1;
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#[cfg(any(stm32wl, stm32wb))]
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#[cfg(any(stm32wl5x, stm32wb))]
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let hclk3 = sys_clk / config.shared_ahb_pre;
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// Set flash wait states
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#[cfg(any(stm32l0, stm32l1))]
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let latency = match (config.voltage_scale, sys_clk.0) {
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(VoltageScale::RANGE1, ..=16_000_000) => false,
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(VoltageScale::RANGE2, ..=8_000_000) => false,
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(VoltageScale::RANGE3, ..=4_200_000) => false,
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_ => true,
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};
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#[cfg(stm32l4)]
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let latency = match hclk1.0 {
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0..=16_000_000 => 0,
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@ -330,6 +346,10 @@ pub(crate) unsafe fn init(config: Config) {
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_ => 4,
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};
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#[cfg(stm32l1)]
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FLASH.acr().write(|w| w.set_acc64(true));
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#[cfg(not(stm32l5))]
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FLASH.acr().modify(|w| w.set_prften(true));
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FLASH.acr().modify(|w| w.set_latency(latency));
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while FLASH.acr().read().latency() != latency {}
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@ -341,9 +361,7 @@ pub(crate) unsafe fn init(config: Config) {
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});
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while RCC.cfgr().read().sws() != config.mux {}
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#[cfg(stm32l5)]
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RCC.ccipr1().modify(|w| w.set_adcsel(config.adc_clock_source));
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#[cfg(not(stm32l5))]
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#[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
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RCC.ccipr().modify(|w| w.set_adcsel(config.adc_clock_source));
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#[cfg(any(stm32wl, stm32wb))]
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@ -361,7 +379,9 @@ pub(crate) unsafe fn init(config: Config) {
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set_freqs(Clocks {
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sys: sys_clk,
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hclk1,
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#[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
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hclk2,
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#[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
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hclk3,
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pclk1,
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pclk2,
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@ -389,6 +409,12 @@ pub(crate) unsafe fn init(config: Config) {
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});
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}
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#[cfg(any(stm32l0, stm32l1))]
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fn msirange_to_hertz(range: MSIRange) -> Hertz {
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Hertz(32_768 * (1 << (range as u8 + 1)))
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}
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#[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
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fn msirange_to_hertz(range: MSIRange) -> Hertz {
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match range {
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MSIRange::RANGE100K => Hertz(100_000),
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@ -407,20 +433,6 @@ fn msirange_to_hertz(range: MSIRange) -> Hertz {
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}
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}
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struct PllInput {
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hsi: Option<Hertz>,
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hse: Option<Hertz>,
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msi: Option<Hertz>,
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}
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#[allow(unused)]
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#[derive(Default)]
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struct PllOutput {
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p: Option<Hertz>,
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q: Option<Hertz>,
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r: Option<Hertz>,
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}
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#[derive(PartialEq, Eq, Clone, Copy)]
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enum PllInstance {
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Pll,
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@ -449,7 +461,113 @@ fn pll_enable(instance: PllInstance, enabled: bool) {
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}
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}
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fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> PllOutput {
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pub use pll::*;
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#[cfg(any(stm32l0, stm32l1))]
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mod pll {
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use super::{pll_enable, PllInstance};
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pub use crate::pac::rcc::vals::{Plldiv as PllDiv, Pllmul as PllMul, Pllsrc as PllSource};
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use crate::pac::RCC;
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use crate::time::Hertz;
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#[derive(Clone, Copy)]
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pub struct Pll {
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/// PLL source
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pub source: PllSource,
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/// PLL multiplication factor.
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pub mul: PllMul,
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/// PLL main output division factor.
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pub div: PllDiv,
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}
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pub(super) struct PllInput {
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pub hsi: Option<Hertz>,
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pub hse: Option<Hertz>,
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}
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#[allow(unused)]
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#[derive(Default)]
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pub(super) struct PllOutput {
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pub r: Option<Hertz>,
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pub clk48: Option<Hertz>,
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}
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pub(super) fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> PllOutput {
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// Disable PLL
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pll_enable(instance, false);
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let Some(pll) = config else { return PllOutput::default() };
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let pll_src = match pll.source {
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PllSource::HSE => unwrap!(input.hse),
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PllSource::HSI => unwrap!(input.hsi),
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};
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let vco_freq = pll_src * pll.mul;
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let r = vco_freq / pll.div;
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let clk48 = (vco_freq == Hertz(96_000_000)).then_some(Hertz(48_000_000));
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assert!(r <= Hertz(32_000_000));
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RCC.cfgr().write(move |w| {
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w.set_pllmul(pll.mul);
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w.set_plldiv(pll.div);
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w.set_pllsrc(pll.source);
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});
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// Enable PLL
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pll_enable(instance, true);
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PllOutput { r: Some(r), clk48 }
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}
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}
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#[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
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mod pll {
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use super::{pll_enable, PllInstance};
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pub use crate::pac::rcc::vals::{
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Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc as PllSource,
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};
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use crate::pac::RCC;
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use crate::time::Hertz;
|
||||
|
||||
#[derive(Clone, Copy)]
|
||||
pub struct Pll {
|
||||
/// PLL source
|
||||
pub source: PllSource,
|
||||
|
||||
/// PLL pre-divider (DIVM).
|
||||
pub prediv: PllPreDiv,
|
||||
|
||||
/// PLL multiplication factor.
|
||||
pub mul: PllMul,
|
||||
|
||||
/// PLL P division factor. If None, PLL P output is disabled.
|
||||
pub divp: Option<PllPDiv>,
|
||||
/// PLL Q division factor. If None, PLL Q output is disabled.
|
||||
pub divq: Option<PllQDiv>,
|
||||
/// PLL R division factor. If None, PLL R output is disabled.
|
||||
pub divr: Option<PllRDiv>,
|
||||
}
|
||||
|
||||
pub(super) struct PllInput {
|
||||
pub hsi: Option<Hertz>,
|
||||
pub hse: Option<Hertz>,
|
||||
pub msi: Option<Hertz>,
|
||||
}
|
||||
|
||||
#[allow(unused)]
|
||||
#[derive(Default)]
|
||||
pub(super) struct PllOutput {
|
||||
pub p: Option<Hertz>,
|
||||
pub q: Option<Hertz>,
|
||||
pub r: Option<Hertz>,
|
||||
}
|
||||
|
||||
pub(super) fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> PllOutput {
|
||||
// Disable PLL
|
||||
pll_enable(instance, false);
|
||||
|
||||
@ -457,13 +575,11 @@ fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> Pll
|
||||
|
||||
let pll_src = match pll.source {
|
||||
PllSource::DISABLE => panic!("must not select PLL source as DISABLE"),
|
||||
PllSource::HSE => input.hse,
|
||||
PllSource::HSI => input.hsi,
|
||||
PllSource::MSI => input.msi,
|
||||
PllSource::HSE => unwrap!(input.hse),
|
||||
PllSource::HSI => unwrap!(input.hsi),
|
||||
PllSource::MSI => unwrap!(input.msi),
|
||||
};
|
||||
|
||||
let pll_src = pll_src.unwrap();
|
||||
|
||||
let vco_freq = pll_src / pll.prediv * pll.mul;
|
||||
|
||||
let p = pll.divp.map(|div| vco_freq / div);
|
||||
@ -523,3 +639,4 @@ fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> Pll
|
||||
|
||||
PllOutput { p, q, r }
|
||||
}
|
||||
}
|
||||
@ -1,190 +0,0 @@
|
||||
pub use crate::pac::pwr::vals::Vos as VoltageScale;
|
||||
pub use crate::pac::rcc::vals::{
|
||||
Hpre as AHBPrescaler, Msirange as MSIRange, Plldiv as PllDiv, Pllmul as PllMul, Pllsrc as PllSource,
|
||||
Ppre as APBPrescaler, Sw as ClockSrc,
|
||||
};
|
||||
use crate::pac::{FLASH, PWR, RCC};
|
||||
use crate::rcc::{set_freqs, Clocks};
|
||||
use crate::time::Hertz;
|
||||
|
||||
/// HSI speed
|
||||
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
|
||||
|
||||
#[derive(Clone, Copy, Eq, PartialEq)]
|
||||
pub enum HseMode {
|
||||
/// crystal/ceramic oscillator (HSEBYP=0)
|
||||
Oscillator,
|
||||
/// external analog clock (low swing) (HSEBYP=1)
|
||||
Bypass,
|
||||
}
|
||||
|
||||
#[derive(Clone, Copy, Eq, PartialEq)]
|
||||
pub struct Hse {
|
||||
/// HSE frequency.
|
||||
pub freq: Hertz,
|
||||
/// HSE mode.
|
||||
pub mode: HseMode,
|
||||
}
|
||||
|
||||
#[derive(Clone, Copy)]
|
||||
pub struct Pll {
|
||||
/// PLL source
|
||||
pub source: PllSource,
|
||||
|
||||
/// PLL multiplication factor.
|
||||
pub mul: PllMul,
|
||||
|
||||
/// PLL main output division factor.
|
||||
pub div: PllDiv,
|
||||
}
|
||||
|
||||
/// Clocks configutation
|
||||
pub struct Config {
|
||||
// base clock sources
|
||||
pub msi: Option<MSIRange>,
|
||||
pub hsi: bool,
|
||||
pub hse: Option<Hse>,
|
||||
#[cfg(crs)]
|
||||
pub hsi48: Option<super::Hsi48Config>,
|
||||
|
||||
pub pll: Option<Pll>,
|
||||
|
||||
pub mux: ClockSrc,
|
||||
pub ahb_pre: AHBPrescaler,
|
||||
pub apb1_pre: APBPrescaler,
|
||||
pub apb2_pre: APBPrescaler,
|
||||
|
||||
pub ls: super::LsConfig,
|
||||
pub voltage_scale: VoltageScale,
|
||||
}
|
||||
|
||||
impl Default for Config {
|
||||
#[inline]
|
||||
fn default() -> Config {
|
||||
Config {
|
||||
msi: Some(MSIRange::RANGE5),
|
||||
hse: None,
|
||||
hsi: false,
|
||||
#[cfg(crs)]
|
||||
hsi48: Some(Default::default()),
|
||||
|
||||
pll: None,
|
||||
|
||||
mux: ClockSrc::MSI,
|
||||
ahb_pre: AHBPrescaler::DIV1,
|
||||
apb1_pre: APBPrescaler::DIV1,
|
||||
apb2_pre: APBPrescaler::DIV1,
|
||||
voltage_scale: VoltageScale::RANGE1,
|
||||
ls: Default::default(),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub(crate) unsafe fn init(config: Config) {
|
||||
// Set voltage scale
|
||||
while PWR.csr().read().vosf() {}
|
||||
PWR.cr().write(|w| w.set_vos(config.voltage_scale));
|
||||
while PWR.csr().read().vosf() {}
|
||||
|
||||
let rtc = config.ls.init();
|
||||
|
||||
let msi = config.msi.map(|range| {
|
||||
RCC.icscr().modify(|w| w.set_msirange(range));
|
||||
|
||||
RCC.cr().modify(|w| w.set_msion(true));
|
||||
while !RCC.cr().read().msirdy() {}
|
||||
|
||||
Hertz(32_768 * (1 << (range as u8 + 1)))
|
||||
});
|
||||
|
||||
let hsi = config.hsi.then(|| {
|
||||
RCC.cr().modify(|w| w.set_hsion(true));
|
||||
while !RCC.cr().read().hsirdy() {}
|
||||
|
||||
HSI_FREQ
|
||||
});
|
||||
|
||||
let hse = config.hse.map(|hse| {
|
||||
RCC.cr().modify(|w| {
|
||||
w.set_hsebyp(hse.mode == HseMode::Bypass);
|
||||
w.set_hseon(true);
|
||||
});
|
||||
while !RCC.cr().read().hserdy() {}
|
||||
|
||||
hse.freq
|
||||
});
|
||||
|
||||
let pll = config.pll.map(|pll| {
|
||||
let freq = match pll.source {
|
||||
PllSource::HSE => hse.unwrap(),
|
||||
PllSource::HSI => hsi.unwrap(),
|
||||
};
|
||||
|
||||
// Disable PLL
|
||||
RCC.cr().modify(|w| w.set_pllon(false));
|
||||
while RCC.cr().read().pllrdy() {}
|
||||
|
||||
let freq = freq * pll.mul / pll.div;
|
||||
|
||||
assert!(freq <= Hertz(32_000_000));
|
||||
|
||||
RCC.cfgr().write(move |w| {
|
||||
w.set_pllmul(pll.mul);
|
||||
w.set_plldiv(pll.div);
|
||||
w.set_pllsrc(pll.source);
|
||||
});
|
||||
|
||||
// Enable PLL
|
||||
RCC.cr().modify(|w| w.set_pllon(true));
|
||||
while !RCC.cr().read().pllrdy() {}
|
||||
|
||||
freq
|
||||
});
|
||||
|
||||
let sys_clk = match config.mux {
|
||||
ClockSrc::HSE => hse.unwrap(),
|
||||
ClockSrc::HSI => hsi.unwrap(),
|
||||
ClockSrc::MSI => msi.unwrap(),
|
||||
ClockSrc::PLL1_P => pll.unwrap(),
|
||||
};
|
||||
|
||||
let wait_states = match (config.voltage_scale, sys_clk.0) {
|
||||
(VoltageScale::RANGE1, ..=16_000_000) => 0,
|
||||
(VoltageScale::RANGE2, ..=8_000_000) => 0,
|
||||
(VoltageScale::RANGE3, ..=4_200_000) => 0,
|
||||
_ => 1,
|
||||
};
|
||||
|
||||
#[cfg(stm32l1)]
|
||||
FLASH.acr().write(|w| w.set_acc64(true));
|
||||
FLASH.acr().modify(|w| w.set_prften(true));
|
||||
FLASH.acr().modify(|w| w.set_latency(wait_states != 0));
|
||||
|
||||
RCC.cfgr().modify(|w| {
|
||||
w.set_sw(config.mux);
|
||||
w.set_hpre(config.ahb_pre);
|
||||
w.set_ppre1(config.apb1_pre);
|
||||
w.set_ppre2(config.apb2_pre);
|
||||
});
|
||||
|
||||
let hclk1 = sys_clk / config.ahb_pre;
|
||||
let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk1, config.apb1_pre);
|
||||
let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk1, config.apb2_pre);
|
||||
|
||||
#[cfg(crs)]
|
||||
let _hsi48 = config.hsi48.map(|config| {
|
||||
// Select HSI48 as USB clock
|
||||
RCC.ccipr().modify(|w| w.set_hsi48msel(true));
|
||||
super::init_hsi48(config)
|
||||
});
|
||||
|
||||
set_freqs(Clocks {
|
||||
sys: sys_clk,
|
||||
hclk1,
|
||||
pclk1,
|
||||
pclk2,
|
||||
pclk1_tim,
|
||||
pclk2_tim,
|
||||
rtc,
|
||||
});
|
||||
}
|
||||
@ -23,8 +23,7 @@ pub use hsi48::*;
|
||||
#[cfg_attr(rcc_g0, path = "g0.rs")]
|
||||
#[cfg_attr(rcc_g4, path = "g4.rs")]
|
||||
#[cfg_attr(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7rm0433, rcc_h7ab), path = "h.rs")]
|
||||
#[cfg_attr(any(rcc_l0, rcc_l0_v2, rcc_l1), path = "l0l1.rs")]
|
||||
#[cfg_attr(any(rcc_l4, rcc_l4plus, rcc_l5, rcc_wl5, rcc_wle, rcc_wb), path = "l4l5.rs")]
|
||||
#[cfg_attr(any(stm32l0, stm32l1, stm32l4, stm32l5, stm32wb, stm32wl), path = "l.rs")]
|
||||
#[cfg_attr(rcc_u5, path = "u5.rs")]
|
||||
#[cfg_attr(rcc_wba, path = "wba.rs")]
|
||||
mod _version;
|
||||
|
||||
@ -466,7 +466,7 @@ pub fn config() -> Config {
|
||||
mul: PllMul::MUL4,
|
||||
div: PllDiv::DIV2, // 32Mhz clock (16 * 4 / 2)
|
||||
});
|
||||
config.rcc.mux = ClockSrc::PLL1_P;
|
||||
config.rcc.mux = ClockSrc::PLL1_R;
|
||||
}
|
||||
|
||||
#[cfg(any(feature = "stm32l152re"))]
|
||||
@ -478,7 +478,7 @@ pub fn config() -> Config {
|
||||
mul: PllMul::MUL4,
|
||||
div: PllDiv::DIV2, // 32Mhz clock (16 * 4 / 2)
|
||||
});
|
||||
config.rcc.mux = ClockSrc::PLL1_P;
|
||||
config.rcc.mux = ClockSrc::PLL1_R;
|
||||
}
|
||||
|
||||
config
|
||||
|
||||
Loading…
Reference in New Issue
Block a user