Adjust to DMA1EN in the rcc for l0.
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@ -170,7 +170,7 @@ impl<'d> Rcc<'d> {
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pub fn enable_debug_wfe(&mut self, _dbg: &mut peripherals::DBGMCU, enable_dma: bool) {
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pub fn enable_debug_wfe(&mut self, _dbg: &mut peripherals::DBGMCU, enable_dma: bool) {
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// NOTE(unsafe) We have exclusive access to the RCC and DBGMCU
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// NOTE(unsafe) We have exclusive access to the RCC and DBGMCU
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unsafe {
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unsafe {
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pac::RCC.ahbenr().modify(|w| w.set_dmaen(enable_dma));
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pac::RCC.ahbenr().modify(|w| w.set_dma1en(enable_dma));
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pac::DBGMCU.cr().modify(|w| {
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pac::DBGMCU.cr().modify(|w| {
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w.set_dbg_sleep(true);
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w.set_dbg_sleep(true);
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Submodule stm32-data updated: 5c3d2df911...9ff09761f3
@ -390,8 +390,8 @@ pub fn gen(options: Options) {
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if let Some(clock_prefix) = clock_prefix {
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if let Some(clock_prefix) = clock_prefix {
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// Workaround for clock registers being split on some chip families. Assume fields are
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// Workaround for clock registers being split on some chip families. Assume fields are
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// named after peripheral and look for first field matching and use that register.
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// named after peripheral and look for first field matching and use that register.
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let mut en = find_reg_for_field(&rcc, clock_prefix, &format!("{}EN", name));
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let en = find_reg_for_field(&rcc, clock_prefix, &format!("{}EN", name));
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let mut rst = find_reg_for_field(&rcc, clock_prefix, &format!("{}RST", name));
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let rst = find_reg_for_field(&rcc, clock_prefix, &format!("{}RST", name));
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match (en, rst) {
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match (en, rst) {
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(Some((enable_reg, enable_field)), Some((reset_reg, reset_field))) => {
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(Some((enable_reg, enable_field)), Some((reset_reg, reset_field))) => {
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