nrf/usb: fix control out transfers getting corrupted due to ep0rcvout sticking from earlier.
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5fd55f9529
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0764fad587
@ -525,10 +525,6 @@ unsafe fn read_dma<T: Instance>(i: usize, buf: &mut [u8]) -> Result<usize, Endpo
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return Err(EndpointError::BufferOverflow);
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return Err(EndpointError::BufferOverflow);
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}
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}
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if i == 0 {
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regs.events_ep0datadone.reset();
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}
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let epout = [
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let epout = [
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®s.epout0,
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®s.epout0,
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®s.epout1,
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®s.epout1,
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@ -639,7 +635,7 @@ pub struct ControlPipe<'d, T: Instance> {
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}
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}
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impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
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impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
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type SetupFuture<'a> = impl Future<Output = Request> + 'a where Self: 'a;
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type SetupFuture<'a> = impl Future<Output = [u8;8]> + 'a where Self: 'a;
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type DataOutFuture<'a> = impl Future<Output = Result<usize, EndpointError>> + 'a where Self: 'a;
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type DataOutFuture<'a> = impl Future<Output = Result<usize, EndpointError>> + 'a where Self: 'a;
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type DataInFuture<'a> = impl Future<Output = Result<(), EndpointError>> + 'a where Self: 'a;
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type DataInFuture<'a> = impl Future<Output = Result<(), EndpointError>> + 'a where Self: 'a;
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@ -651,11 +647,11 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
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async move {
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async move {
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let regs = T::regs();
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let regs = T::regs();
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// Reset shorts
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regs.shorts.write(|w| w);
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// Wait for SETUP packet
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// Wait for SETUP packet
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regs.intenset.write(|w| {
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regs.intenset.write(|w| w.ep0setup().set());
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w.ep0setup().set();
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w.ep0datadone().set()
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});
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poll_fn(|cx| {
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poll_fn(|cx| {
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EP0_WAKER.register(cx.waker());
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EP0_WAKER.register(cx.waker());
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let regs = T::regs();
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let regs = T::regs();
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@ -667,8 +663,6 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
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})
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})
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.await;
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.await;
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// Reset shorts
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regs.shorts.write(|w| w);
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regs.events_ep0setup.reset();
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regs.events_ep0setup.reset();
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let mut buf = [0; 8];
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let mut buf = [0; 8];
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@ -689,6 +683,9 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
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async move {
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async move {
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let regs = T::regs();
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let regs = T::regs();
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regs.events_ep0datadone.reset();
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// This starts a RX on EP0. events_ep0datadone notifies when done.
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regs.tasks_ep0rcvout
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regs.tasks_ep0rcvout
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.write(|w| w.tasks_ep0rcvout().set_bit());
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.write(|w| w.tasks_ep0rcvout().set_bit());
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@ -723,13 +720,13 @@ impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
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async move {
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async move {
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let regs = T::regs();
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let regs = T::regs();
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regs.events_ep0datadone.reset();
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regs.events_ep0datadone.reset();
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unsafe {
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write_dma::<T>(0, buf);
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}
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regs.shorts
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regs.shorts
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.write(|w| w.ep0datadone_ep0status().bit(last_packet));
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.write(|w| w.ep0datadone_ep0status().bit(last_packet));
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// This starts a TX on EP0. events_ep0datadone notifies when done.
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unsafe { write_dma::<T>(0, buf) }
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regs.intenset.write(|w| {
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regs.intenset.write(|w| {
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w.usbreset().set();
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w.usbreset().set();
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w.ep0setup().set();
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w.ep0setup().set();
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