From 091e7e1f98c4220889b6fbf4f388320e21f43494 Mon Sep 17 00:00:00 2001
From: Tobias Pisani <tobias.pisani@moveinnovation.dk>
Date: Sat, 9 Oct 2021 11:40:39 +0200
Subject: [PATCH] Generate USART pin definitions for stm32f1

---
 embassy-stm32/src/gpio.rs      | 12 +++++-----
 embassy-stm32/src/usart/mod.rs | 40 +++++++++++++++++++++++++++++++++-
 2 files changed, 45 insertions(+), 7 deletions(-)

diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs
index 3a8117e9..5c48b5be 100644
--- a/embassy-stm32/src/gpio.rs
+++ b/embassy-stm32/src/gpio.rs
@@ -401,15 +401,15 @@ pub(crate) mod sealed {
             // F1 uses the AFIO register for remapping.
             // For now, this is not implemented, so af_num is ignored
             // _af_num should be zero here, since it is not set by stm32-data
-            let r = pin.block();
-            let n = pin.pin() as usize;
+            let r = self.block();
+            let n = self._pin() as usize;
             let crlh = if n < 8 { 0 } else { 1 };
             match af_type {
                 // TODO: Do we need to configure input AF pins differently?
-                AfType::OutputPushPull => {
+                AFType::OutputPushPull => {
                     r.cr(crlh).modify(|w| w.set_cnf(n % 8, vals::Cnf::PUSHPULL));
                 }
-                AfType::OutputOpenDrain => r
+                AFType::OutputOpenDrain => r
                     .cr(crlh)
                     .modify(|w| w.set_cnf(n % 8, vals::Cnf::OPENDRAIN)),
             }
@@ -422,10 +422,10 @@ pub(crate) mod sealed {
                 .afr(pin / 8)
                 .modify(|w| w.set_afr(pin % 8, vals::Afr(af_num)));
             match af_type {
-                AfType::OutputPushPull => {
+                AFType::OutputPushPull => {
                     block.otyper().modify(|w| w.set_ot(pin, vals::Ot::PUSHPULL))
                 }
-                AfType::OutputOpenDrain => block
+                AFType::OutputOpenDrain => block
                     .otyper()
                     .modify(|w| w.set_ot(pin, vals::Ot::OPENDRAIN)),
             }
diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs
index e64f8d1d..a6955729 100644
--- a/embassy-stm32/src/usart/mod.rs
+++ b/embassy-stm32/src/usart/mod.rs
@@ -127,7 +127,6 @@ crate::pac::interrupts!(
     };
 );
 
-#[cfg(not(rcc_f1))]
 macro_rules! impl_pin {
     ($inst:ident, $pin:ident, $signal:ident, $af:expr) => {
         impl sealed::$signal<peripherals::$inst> for peripherals::$pin {
@@ -140,6 +139,7 @@ macro_rules! impl_pin {
     };
 }
 
+#[cfg(not(rcc_f1))]
 crate::pac::peripheral_pins!(
 
     // USART
@@ -177,6 +177,44 @@ crate::pac::peripheral_pins!(
     };
 );
 
+#[cfg(rcc_f1)]
+crate::pac::peripheral_pins!(
+
+    // USART
+    ($inst:ident, usart, USART, $pin:ident, TX) => {
+        impl_pin!($inst, $pin, TxPin, 0);
+    };
+    ($inst:ident, usart, USART, $pin:ident, RX) => {
+        impl_pin!($inst, $pin, RxPin, 0);
+    };
+    ($inst:ident, usart, USART, $pin:ident, CTS) => {
+        impl_pin!($inst, $pin, CtsPin, 0);
+    };
+    ($inst:ident, usart, USART, $pin:ident, RTS) => {
+        impl_pin!($inst, $pin, RtsPin, 0);
+    };
+    ($inst:ident, usart, USART, $pin:ident, CK) => {
+        impl_pin!($inst, $pin, CkPin, 0);
+    };
+
+    // UART
+    ($inst:ident, uart, UART, $pin:ident, TX) => {
+        impl_pin!($inst, $pin, TxPin, 0);
+    };
+    ($inst:ident, uart, UART, $pin:ident, RX) => {
+        impl_pin!($inst, $pin, RxPin, 0);
+    };
+    ($inst:ident, uart, UART, $pin:ident, CTS) => {
+        impl_pin!($inst, $pin, CtsPin, 0);
+    };
+    ($inst:ident, uart, UART, $pin:ident, RTS) => {
+        impl_pin!($inst, $pin, RtsPin, 0);
+    };
+    ($inst:ident, uart, UART, $pin:ident, CK) => {
+        impl_pin!($inst, $pin, CkPin, 0);
+    };
+);
+
 macro_rules! impl_dma {
     ($inst:ident, {dmamux: $dmamux:ident}, $signal:ident, $request:expr) => {
         impl<T> sealed::$signal<peripherals::$inst> for T