From 0b607ca80a990d7d3696cf95389e35e1dc5dc761 Mon Sep 17 00:00:00 2001 From: Thales Fragoso Date: Sat, 1 May 2021 21:19:14 -0300 Subject: [PATCH] Initial H7 sdmmc support --- .vscode/settings.json | 13 + embassy-stm32/Cargo.toml | 5 +- embassy-stm32/gen.py | 27 +- embassy-stm32/src/chip/stm32h723ve.rs | 885 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h723vg.rs | 885 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h723ze.rs | 885 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h723zg.rs | 885 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h725ae.rs | 885 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h725ag.rs | 885 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h725ie.rs | 885 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h725ig.rs | 885 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h725re.rs | 884 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h725rg.rs | 884 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h725ve.rs | 885 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h725vg.rs | 885 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h725ze.rs | 885 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h725zg.rs | 885 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h730ab.rs | 894 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h730ib.rs | 894 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h730vb.rs | 894 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h730zb.rs | 894 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h733vg.rs | 894 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h733zg.rs | 894 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h735ag.rs | 894 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h735ig.rs | 894 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h735rg.rs | 893 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h735vg.rs | 894 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h735zg.rs | 894 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h742ag.rs | 892 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h742ai.rs | 892 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h742bg.rs | 892 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h742bi.rs | 892 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h742ig.rs | 892 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h742ii.rs | 892 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h742vg.rs | 892 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h742vi.rs | 892 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h742xg.rs | 892 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h742xi.rs | 892 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h742zg.rs | 892 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h742zi.rs | 892 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h743ag.rs | 901 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h743ai.rs | 901 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h743bg.rs | 901 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h743bi.rs | 901 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h743ig.rs | 901 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h743ii.rs | 901 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h743vg.rs | 901 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h743vi.rs | 901 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h743xg.rs | 901 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h743xi.rs | 901 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h743zg.rs | 901 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h743zi.rs | 901 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h745bg.rs | 915 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h745bi.rs | 915 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h745ig.rs | 915 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h745ii.rs | 915 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h745xg.rs | 915 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h745xi.rs | 915 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h745zg.rs | 915 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h745zi.rs | 915 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h747ag.rs | 918 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h747ai.rs | 918 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h747bg.rs | 918 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h747bi.rs | 918 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h747ig.rs | 918 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h747ii.rs | 918 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h747xg.rs | 918 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h747xi.rs | 918 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h747zi.rs | 918 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h750ib.rs | 904 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h750vb.rs | 904 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h750xb.rs | 904 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h750zb.rs | 904 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h753ai.rs | 904 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h753bi.rs | 904 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h753ii.rs | 904 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h753vi.rs | 904 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h753xi.rs | 904 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h753zi.rs | 904 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h755bi.rs | 919 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h755ii.rs | 919 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h755xi.rs | 919 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h755zi.rs | 919 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h757ai.rs | 922 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h757bi.rs | 922 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h757ii.rs | 922 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h757xi.rs | 922 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h757zi.rs | 921 +++++++++++++++++++++ embassy-stm32/src/chip/stm32h7a3ag.rs | 886 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7a3ai.rs | 886 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7a3ig.rs | 886 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7a3ii.rs | 886 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7a3lg.rs | 886 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7a3li.rs | 886 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7a3ng.rs | 886 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7a3ni.rs | 886 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7a3qi.rs | 886 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7a3rg.rs | 885 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7a3ri.rs | 885 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7a3vg.rs | 886 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7a3vi.rs | 886 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7a3zg.rs | 886 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7a3zi.rs | 886 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7b0ab.rs | 895 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7b0ib.rs | 895 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7b0rb.rs | 894 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7b0vb.rs | 895 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7b0zb.rs | 895 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7b3ai.rs | 895 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7b3ii.rs | 895 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7b3li.rs | 895 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7b3ni.rs | 895 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7b3qi.rs | 895 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7b3ri.rs | 894 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7b3vi.rs | 895 ++++++++++++++++++++ embassy-stm32/src/chip/stm32h7b3zi.rs | 895 ++++++++++++++++++++ embassy-stm32/src/chip/stm32l412c8.rs | 415 ++++++++++ embassy-stm32/src/chip/stm32l412cb.rs | 415 ++++++++++ embassy-stm32/src/chip/stm32l412k8.rs | 415 ++++++++++ embassy-stm32/src/chip/stm32l412kb.rs | 415 ++++++++++ embassy-stm32/src/chip/stm32l412r8.rs | 415 ++++++++++ embassy-stm32/src/chip/stm32l412rb.rs | 415 ++++++++++ embassy-stm32/src/chip/stm32l412t8.rs | 415 ++++++++++ embassy-stm32/src/chip/stm32l412tb.rs | 415 ++++++++++ embassy-stm32/src/chip/stm32l422cb.rs | 419 ++++++++++ embassy-stm32/src/chip/stm32l422kb.rs | 418 ++++++++++ embassy-stm32/src/chip/stm32l422rb.rs | 419 ++++++++++ embassy-stm32/src/chip/stm32l422tb.rs | 418 ++++++++++ embassy-stm32/src/chip/stm32l431cb.rs | 457 +++++++++++ embassy-stm32/src/chip/stm32l431cc.rs | 457 +++++++++++ embassy-stm32/src/chip/stm32l431kb.rs | 456 +++++++++++ embassy-stm32/src/chip/stm32l431kc.rs | 456 +++++++++++ embassy-stm32/src/chip/stm32l431rb.rs | 457 +++++++++++ embassy-stm32/src/chip/stm32l431rc.rs | 457 +++++++++++ embassy-stm32/src/chip/stm32l431vc.rs | 457 +++++++++++ embassy-stm32/src/chip/stm32l432kb.rs | 411 ++++++++++ embassy-stm32/src/chip/stm32l432kc.rs | 411 ++++++++++ embassy-stm32/src/chip/stm32l433cb.rs | 463 +++++++++++ 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embassy-stm32/src/h7/rcc.rs | 36 + embassy-stm32/src/lib.rs | 13 + embassy-stm32/src/pac/mod.rs | 113 +++ embassy-stm32/src/pac/stm32h723ve.rs | 906 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h723vg.rs | 906 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h723ze.rs | 906 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h723zg.rs | 906 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h725ae.rs | 906 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h725ag.rs | 906 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h725ie.rs | 906 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h725ig.rs | 906 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h725re.rs | 906 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h725rg.rs | 906 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h725ve.rs | 906 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h725vg.rs | 906 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h725ze.rs | 906 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h725zg.rs | 906 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embassy-stm32/src/pac/stm32h747bg.rs | 941 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h747bi.rs | 941 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h747ig.rs | 941 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h747ii.rs | 941 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h747xg.rs | 941 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h747xi.rs | 941 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h747zi.rs | 941 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h750ib.rs | 927 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h750vb.rs | 927 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h750xb.rs | 927 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h750zb.rs | 927 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h753ai.rs | 927 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h753bi.rs | 927 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h753ii.rs | 927 +++++++++++++++++++++ embassy-stm32/src/pac/stm32h753vi.rs | 927 +++++++++++++++++++++ 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embassy-stm32/src/pac/stm32h7b3vi.rs create mode 100644 embassy-stm32/src/pac/stm32h7b3zi.rs create mode 100644 embassy-stm32/src/sdmmc_v2.rs diff --git a/.vscode/settings.json b/.vscode/settings.json index 17293413..80af21f1 100644 --- a/.vscode/settings.json +++ b/.vscode/settings.json @@ -1,3 +1,16 @@ { "editor.formatOnSave": true, + "rust-analyzer.cargo.allFeatures": false, + "rust-analyzer.checkOnSave.allFeatures": false, + "rust-analyzer.checkOnSave.allTargets": false, + "rust-analyzer.cargo.target": "thumbv7em-none-eabihf", + "rust-analyzer.checkOnSave.target": "thumbv7em-none-eabihf", + "rust-analyzer.procMacro.enable": true, + "rust-analyzer.cargo.loadOutDirsFromCheck": true, + "files.watcherExclude": { + "**/.git/objects/**": true, + "**/.git/subtree-cache/**": true, + "**/target/**": true, + "**/embassy-stm32/src/chip/**": true, + } } \ No newline at end of file diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml index f4f5b085..c2e6c7a5 100644 --- a/embassy-stm32/Cargo.toml +++ b/embassy-stm32/Cargo.toml @@ -8,6 +8,7 @@ edition = "2018" embassy = { version = "0.1.0", path = "../embassy" } embassy-macros = { version = "0.1.0", path = "../embassy-macros" } embassy-extras = {version = "0.1.0", path = "../embassy-extras" } +embassy-traits = {version = "0.1.0", path = "../embassy-traits" } defmt = { version = "0.2.0", optional = true } log = { version = "0.4.11", optional = true } @@ -15,12 +16,14 @@ cortex-m-rt = { version = "0.6.13", features = ["device"] } cortex-m = "0.7.1" embedded-hal = { version = "0.2.4" } futures = { version = "0.3.5", default-features = false, features = ["async-await"] } -rand_core = { version = "0.6.2", optional=true} +rand_core = { version = "0.6.2", optional = true } +sdio-host = "0.5.0" [build-dependencies] regex = "1.4.6" [features] +default = ["stm32h750vb", "defmt-debug", "defmt"] defmt-trace = [ ] defmt-debug = [ ] defmt-info = [ ] diff --git a/embassy-stm32/gen.py b/embassy-stm32/gen.py index 056d66ec..15bb8ace 100644 --- a/embassy-stm32/gen.py +++ b/embassy-stm32/gen.py @@ -14,7 +14,7 @@ os.chdir(dname) # ======= load chips chips = {} for f in sorted(glob('stm32-data/data/chips/*.yaml')): - if 'STM32F4' not in f and 'STM32L4' not in f: + if 'STM32F4' not in f and 'STM32L4' not in f and 'STM32H7' not in f: continue with open(f, 'r') as f: chip = yaml.load(f, Loader=yaml.CSafeLoader) @@ -150,6 +150,31 @@ for chip in chips.values(): peripheral_names.append(channel) f.write(f'impl_dma_channel!({channel}, {name}, {ch_num});') + if peri['block'] == 'sdmmc_v2/SDMMC': + f.write(f'impl_sdmmc!({name}, 0x{peri["address"]:x});') + for pin, funcs in af.items(): + if pin in pins: + if func := funcs.get(f'{name}_CK'): + f.write(f'impl_sdmmc_pin!({name}, CkPin, {pin}, {func});') + if func := funcs.get(f'{name}_CMD'): + f.write(f'impl_sdmmc_pin!({name}, CmdPin, {pin}, {func});') + if func := funcs.get(f'{name}_D0'): + f.write(f'impl_sdmmc_pin!({name}, D0Pin, {pin}, {func});') + if func := funcs.get(f'{name}_D1'): + f.write(f'impl_sdmmc_pin!({name}, D1Pin, {pin}, {func});') + if func := funcs.get(f'{name}_D2'): + f.write(f'impl_sdmmc_pin!({name}, D2Pin, {pin}, {func});') + if func := funcs.get(f'{name}_D3'): + f.write(f'impl_sdmmc_pin!({name}, D3Pin, {pin}, {func});') + if func := funcs.get(f'{name}_D4'): + f.write(f'impl_sdmmc_pin!({name}, D4Pin, {pin}, {func});') + if func := funcs.get(f'{name}_D5'): + f.write(f'impl_sdmmc_pin!({name}, D5Pin, {pin}, {func});') + if func := funcs.get(f'{name}_D6'): + f.write(f'impl_sdmmc_pin!({name}, D6Pin, {pin}, {func});') + if func := funcs.get(f'{name}_D7'): + f.write(f'impl_sdmmc_pin!({name}, D7Pin, {pin}, {func});') + if not custom_singletons: peripheral_names.append(name) diff --git a/embassy-stm32/src/chip/stm32h723ve.rs b/embassy-stm32/src/chip/stm32h723ve.rs new file mode 100644 index 00000000..11be318c --- /dev/null +++ b/embassy-stm32/src/chip/stm32h723ve.rs @@ -0,0 +1,885 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, DAC1, DCMI, DMA2D, DTS, + ETH, FDCAN1, FDCAN2, FDCAN3, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, + PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, + PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, + PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, + PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, + PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, + PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, + PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, + PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, I2C5, IWDG1, + LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, + SPI3, SPI4, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM23, + TIM24, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, UART9, USART1, USART10, + USART2, USART3, USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h723vg.rs b/embassy-stm32/src/chip/stm32h723vg.rs new file mode 100644 index 00000000..11be318c --- /dev/null +++ b/embassy-stm32/src/chip/stm32h723vg.rs @@ -0,0 +1,885 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, DAC1, DCMI, DMA2D, DTS, + ETH, FDCAN1, FDCAN2, FDCAN3, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, + PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, + PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, + PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, + PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, + PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, + PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, + PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, + PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, I2C5, IWDG1, + LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, + SPI3, SPI4, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM23, + TIM24, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, UART9, USART1, USART10, + USART2, USART3, USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h723ze.rs b/embassy-stm32/src/chip/stm32h723ze.rs new file mode 100644 index 00000000..256d7b48 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h723ze.rs @@ -0,0 +1,885 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, DAC1, DCMI, DMA2D, DTS, + ETH, FDCAN1, FDCAN2, FDCAN3, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, + PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, + PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, + PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, + PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, + PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, + PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, + PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, + PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, I2C5, IWDG1, + LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, + SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, + TIM23, TIM24, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, UART9, USART1, + USART10, USART2, USART3, USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h723zg.rs b/embassy-stm32/src/chip/stm32h723zg.rs new file mode 100644 index 00000000..256d7b48 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h723zg.rs @@ -0,0 +1,885 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, DAC1, DCMI, DMA2D, DTS, + ETH, FDCAN1, FDCAN2, FDCAN3, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, + PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, + PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, + PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, + PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, + PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, + PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, + PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, + PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, I2C5, IWDG1, + LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, + SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, + TIM23, TIM24, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, UART9, USART1, + USART10, USART2, USART3, USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h725ae.rs b/embassy-stm32/src/chip/stm32h725ae.rs new file mode 100644 index 00000000..c1ee7b25 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h725ae.rs @@ -0,0 +1,885 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, DAC1, DCMI, DMA2D, DTS, + ETH, FDCAN1, FDCAN2, FDCAN3, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, + PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, + PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, + PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, + PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, + PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, + PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, + PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, + PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, I2C5, IWDG1, + LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, + SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, + TIM23, TIM24, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, UART9, USART1, + USART2, USART3, USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h725ag.rs b/embassy-stm32/src/chip/stm32h725ag.rs new file mode 100644 index 00000000..c1ee7b25 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h725ag.rs @@ -0,0 +1,885 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, DAC1, DCMI, DMA2D, DTS, + ETH, FDCAN1, FDCAN2, FDCAN3, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, + PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, + PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, + PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, + PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, + PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, + PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, + PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, + PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, I2C5, IWDG1, + LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, + SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, + TIM23, TIM24, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, UART9, USART1, + USART2, USART3, USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h725ie.rs b/embassy-stm32/src/chip/stm32h725ie.rs new file mode 100644 index 00000000..256d7b48 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h725ie.rs @@ -0,0 +1,885 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, DAC1, DCMI, DMA2D, DTS, + ETH, FDCAN1, FDCAN2, FDCAN3, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, + PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, + PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, + PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, + PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, + PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, + PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, + PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, + PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, I2C5, IWDG1, + LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, + SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, + TIM23, TIM24, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, UART9, USART1, + USART10, USART2, USART3, USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h725ig.rs b/embassy-stm32/src/chip/stm32h725ig.rs new file mode 100644 index 00000000..256d7b48 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h725ig.rs @@ -0,0 +1,885 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, DAC1, DCMI, DMA2D, DTS, + ETH, FDCAN1, FDCAN2, FDCAN3, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, + PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, + PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, + PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, + PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, + PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, + PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, + PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, + PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, I2C5, IWDG1, + LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, + SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, + TIM23, TIM24, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, UART9, USART1, + USART10, USART2, USART3, USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h725re.rs b/embassy-stm32/src/chip/stm32h725re.rs new file mode 100644 index 00000000..aa848d4d --- /dev/null +++ b/embassy-stm32/src/chip/stm32h725re.rs @@ -0,0 +1,884 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, DAC1, DCMI, DMA2D, DTS, + FDCAN1, FDCAN2, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, + PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, + PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, + PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, + PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, + PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, + PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, + PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, LPTIM1, LPTIM2, LPTIM3, LPTIM4, + LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, PSSI, PWR, RCC, RNG, + RTC, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, + TIM16, TIM17, TIM2, TIM23, TIM24, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + USART1, USART2, USART3, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h725rg.rs b/embassy-stm32/src/chip/stm32h725rg.rs new file mode 100644 index 00000000..aa848d4d --- /dev/null +++ b/embassy-stm32/src/chip/stm32h725rg.rs @@ -0,0 +1,884 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, DAC1, DCMI, DMA2D, DTS, + FDCAN1, FDCAN2, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, + PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, + PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, + PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, + PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, + PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, + PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, + PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, LPTIM1, LPTIM2, LPTIM3, LPTIM4, + LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, PSSI, PWR, RCC, RNG, + RTC, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, + TIM16, TIM17, TIM2, TIM23, TIM24, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + USART1, USART2, USART3, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h725ve.rs b/embassy-stm32/src/chip/stm32h725ve.rs new file mode 100644 index 00000000..ff8a58db --- /dev/null +++ b/embassy-stm32/src/chip/stm32h725ve.rs @@ -0,0 +1,885 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, DAC1, DCMI, DMA2D, DTS, + ETH, FDCAN1, FDCAN2, FDCAN3, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, + PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, + PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, + PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, + PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, + PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, + PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, + PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, + PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, I2C5, IWDG1, + LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, + SPI3, SPI4, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM23, + TIM24, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, USART1, USART2, USART3, + USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h725vg.rs b/embassy-stm32/src/chip/stm32h725vg.rs new file mode 100644 index 00000000..b9604da9 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h725vg.rs @@ -0,0 +1,885 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, DAC1, DCMI, DMA2D, DTS, + ETH, FDCAN1, FDCAN2, FDCAN3, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, + PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, + PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, + PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, + PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, + PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, + PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, + PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, + PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, I2C5, IWDG1, + LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, + SPI3, SPI4, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM23, + TIM24, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, UART9, USART1, USART2, + USART3, USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h725ze.rs b/embassy-stm32/src/chip/stm32h725ze.rs new file mode 100644 index 00000000..256d7b48 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h725ze.rs @@ -0,0 +1,885 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, DAC1, DCMI, DMA2D, DTS, + ETH, FDCAN1, FDCAN2, FDCAN3, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, + PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, + PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, + PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, + PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, + PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, + PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, + PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, + PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, I2C5, IWDG1, + LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, + SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, + TIM23, TIM24, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, UART9, USART1, + USART10, USART2, USART3, USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h725zg.rs b/embassy-stm32/src/chip/stm32h725zg.rs new file mode 100644 index 00000000..256d7b48 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h725zg.rs @@ -0,0 +1,885 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, DAC1, DCMI, DMA2D, DTS, + ETH, FDCAN1, FDCAN2, FDCAN3, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, + PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, + PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, + PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, + PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, + PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, + PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, + PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, + PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, I2C5, IWDG1, + LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, + SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, + TIM23, TIM24, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, UART9, USART1, + USART10, USART2, USART3, USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h730ab.rs b/embassy-stm32/src/chip/stm32h730ab.rs new file mode 100644 index 00000000..2a14ee4f --- /dev/null +++ b/embassy-stm32/src/chip/stm32h730ab.rs @@ -0,0 +1,894 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, CRYP, DAC1, DCMI, DMA2D, + DTS, ETH, FDCAN1, FDCAN2, FDCAN3, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, + PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, + PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, + PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, + PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, + PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, + PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, + PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, + PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, I2C5, + IWDG1, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, OTFDEC1, OTFDEC2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI4, SDMMC1, + SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, + TIM16, TIM17, TIM2, TIM23, TIM24, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, UART9, USART1, USART2, USART3, USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h730ib.rs b/embassy-stm32/src/chip/stm32h730ib.rs new file mode 100644 index 00000000..696b1231 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h730ib.rs @@ -0,0 +1,894 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, CRYP, DAC1, DCMI, DMA2D, + DTS, ETH, FDCAN1, FDCAN2, FDCAN3, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, + PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, + PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, + PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, + PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, + PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, + PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, + PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, + PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, I2C5, + IWDG1, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, OTFDEC1, OTFDEC2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI4, SDMMC1, + SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, + TIM16, TIM17, TIM2, TIM23, TIM24, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, UART9, USART1, USART10, USART2, USART3, USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h730vb.rs b/embassy-stm32/src/chip/stm32h730vb.rs new file mode 100644 index 00000000..ae3ede17 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h730vb.rs @@ -0,0 +1,894 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, CRYP, DAC1, DCMI, DMA2D, + DTS, ETH, FDCAN1, FDCAN2, FDCAN3, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, + PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, + PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, + PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, + PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, + PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, + PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, + PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, + PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, I2C5, + IWDG1, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, OTFDEC1, OTFDEC2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI4, SDMMC1, + SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, + TIM17, TIM2, TIM23, TIM24, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, + UART9, USART1, USART10, USART2, USART3, USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h730zb.rs b/embassy-stm32/src/chip/stm32h730zb.rs new file mode 100644 index 00000000..696b1231 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h730zb.rs @@ -0,0 +1,894 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, CRYP, DAC1, DCMI, DMA2D, + DTS, ETH, FDCAN1, FDCAN2, FDCAN3, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, + PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, + PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, + PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, + PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, + PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, + PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, + PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, + PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, I2C5, + IWDG1, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, OTFDEC1, OTFDEC2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI4, SDMMC1, + SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, + TIM16, TIM17, TIM2, TIM23, TIM24, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, UART9, USART1, USART10, USART2, USART3, USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h733vg.rs b/embassy-stm32/src/chip/stm32h733vg.rs new file mode 100644 index 00000000..ae3ede17 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h733vg.rs @@ -0,0 +1,894 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, CRYP, DAC1, DCMI, DMA2D, + DTS, ETH, FDCAN1, FDCAN2, FDCAN3, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, + PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, + PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, + PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, + PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, + PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, + PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, + PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, + PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, I2C5, + IWDG1, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, OTFDEC1, OTFDEC2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI4, SDMMC1, + SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, + TIM17, TIM2, TIM23, TIM24, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, + UART9, USART1, USART10, USART2, USART3, USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h733zg.rs b/embassy-stm32/src/chip/stm32h733zg.rs new file mode 100644 index 00000000..696b1231 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h733zg.rs @@ -0,0 +1,894 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, CRYP, DAC1, DCMI, DMA2D, + DTS, ETH, FDCAN1, FDCAN2, FDCAN3, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, + PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, + PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, + PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, + PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, + PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, + PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, + PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, + PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, I2C5, + IWDG1, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, OTFDEC1, OTFDEC2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI4, SDMMC1, + SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, + TIM16, TIM17, TIM2, TIM23, TIM24, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, UART9, USART1, USART10, USART2, USART3, USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h735ag.rs b/embassy-stm32/src/chip/stm32h735ag.rs new file mode 100644 index 00000000..2a14ee4f --- /dev/null +++ b/embassy-stm32/src/chip/stm32h735ag.rs @@ -0,0 +1,894 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, CRYP, DAC1, DCMI, DMA2D, + DTS, ETH, FDCAN1, FDCAN2, FDCAN3, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, + PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, + PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, + PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, + PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, + PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, + PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, + PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, + PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, I2C5, + IWDG1, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, OTFDEC1, OTFDEC2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI4, SDMMC1, + SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, + TIM16, TIM17, TIM2, TIM23, TIM24, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, UART9, USART1, USART2, USART3, USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h735ig.rs b/embassy-stm32/src/chip/stm32h735ig.rs new file mode 100644 index 00000000..696b1231 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h735ig.rs @@ -0,0 +1,894 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, CRYP, DAC1, DCMI, DMA2D, + DTS, ETH, FDCAN1, FDCAN2, FDCAN3, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, + PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, + PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, + PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, + PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, + PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, + PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, + PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, + PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, I2C5, + IWDG1, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, OTFDEC1, OTFDEC2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI4, SDMMC1, + SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, + TIM16, TIM17, TIM2, TIM23, TIM24, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, UART9, USART1, USART10, USART2, USART3, USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h735rg.rs b/embassy-stm32/src/chip/stm32h735rg.rs new file mode 100644 index 00000000..1eb951c4 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h735rg.rs @@ -0,0 +1,893 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, CRYP, DAC1, DCMI, DMA2D, + DTS, FDCAN1, FDCAN2, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, LPTIM1, LPTIM2, + LPTIM3, LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, + OTFDEC1, OTFDEC2, PSSI, PWR, RCC, RNG, RTC, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI6, SWPMI1, + SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM23, TIM24, TIM3, TIM4, TIM5, + TIM6, TIM7, TIM8, UART4, UART5, UART7, USART1, USART2, USART3, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h735vg.rs b/embassy-stm32/src/chip/stm32h735vg.rs new file mode 100644 index 00000000..7843ad5d --- /dev/null +++ b/embassy-stm32/src/chip/stm32h735vg.rs @@ -0,0 +1,894 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, CRYP, DAC1, DCMI, DMA2D, + DTS, ETH, FDCAN1, FDCAN2, FDCAN3, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, + PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, + PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, + PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, + PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, + PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, + PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, + PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, + PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, I2C5, + IWDG1, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, OTFDEC1, OTFDEC2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI4, SDMMC1, + SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, + TIM17, TIM2, TIM23, TIM24, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, + UART9, USART1, USART2, USART3, USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h735zg.rs b/embassy-stm32/src/chip/stm32h735zg.rs new file mode 100644 index 00000000..696b1231 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h735zg.rs @@ -0,0 +1,894 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CORDIC, CRYP, DAC1, DCMI, DMA2D, + DTS, ETH, FDCAN1, FDCAN2, FDCAN3, FMAC, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, + PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, + PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, + PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, + PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, + PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, + PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, + PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, + PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, + PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, I2C5, + IWDG1, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, OTFDEC1, OTFDEC2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI4, SDMMC1, + SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, + TIM16, TIM17, TIM2, TIM23, TIM24, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, UART9, USART1, USART10, USART2, USART3, USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h742ag.rs b/embassy-stm32/src/chip/stm32h742ag.rs new file mode 100644 index 00000000..16c6b22f --- /dev/null +++ b/embassy-stm32/src/chip/stm32h742ag.rs @@ -0,0 +1,892 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, + MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, SAI4, SDMMC1, + SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, USART1, + USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h742ai.rs b/embassy-stm32/src/chip/stm32h742ai.rs new file mode 100644 index 00000000..16c6b22f --- /dev/null +++ b/embassy-stm32/src/chip/stm32h742ai.rs @@ -0,0 +1,892 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, + MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, SAI4, SDMMC1, + SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, USART1, + USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h742bg.rs b/embassy-stm32/src/chip/stm32h742bg.rs new file mode 100644 index 00000000..16c6b22f --- /dev/null +++ b/embassy-stm32/src/chip/stm32h742bg.rs @@ -0,0 +1,892 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, + MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, SAI4, SDMMC1, + SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, USART1, + USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h742bi.rs b/embassy-stm32/src/chip/stm32h742bi.rs new file mode 100644 index 00000000..16c6b22f --- /dev/null +++ b/embassy-stm32/src/chip/stm32h742bi.rs @@ -0,0 +1,892 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, + MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, SAI4, SDMMC1, + SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, USART1, + USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h742ig.rs b/embassy-stm32/src/chip/stm32h742ig.rs new file mode 100644 index 00000000..16c6b22f --- /dev/null +++ b/embassy-stm32/src/chip/stm32h742ig.rs @@ -0,0 +1,892 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, + MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, SAI4, SDMMC1, + SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, USART1, + USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h742ii.rs b/embassy-stm32/src/chip/stm32h742ii.rs new file mode 100644 index 00000000..16c6b22f --- /dev/null +++ b/embassy-stm32/src/chip/stm32h742ii.rs @@ -0,0 +1,892 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, + MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, SAI4, SDMMC1, + SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, USART1, + USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h742vg.rs b/embassy-stm32/src/chip/stm32h742vg.rs new file mode 100644 index 00000000..548d9af4 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h742vg.rs @@ -0,0 +1,892 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, + MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, SAI4, SDMMC1, + SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, + TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, USART1, USART2, + USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h742vi.rs b/embassy-stm32/src/chip/stm32h742vi.rs new file mode 100644 index 00000000..548d9af4 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h742vi.rs @@ -0,0 +1,892 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, + MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, SAI4, SDMMC1, + SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, + TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, USART1, USART2, + USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h742xg.rs b/embassy-stm32/src/chip/stm32h742xg.rs new file mode 100644 index 00000000..16c6b22f --- /dev/null +++ b/embassy-stm32/src/chip/stm32h742xg.rs @@ -0,0 +1,892 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, + MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, SAI4, SDMMC1, + SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, USART1, + USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h742xi.rs b/embassy-stm32/src/chip/stm32h742xi.rs new file mode 100644 index 00000000..16c6b22f --- /dev/null +++ b/embassy-stm32/src/chip/stm32h742xi.rs @@ -0,0 +1,892 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, + MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, SAI4, SDMMC1, + SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, USART1, + USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h742zg.rs b/embassy-stm32/src/chip/stm32h742zg.rs new file mode 100644 index 00000000..16c6b22f --- /dev/null +++ b/embassy-stm32/src/chip/stm32h742zg.rs @@ -0,0 +1,892 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, + MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, SAI4, SDMMC1, + SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, USART1, + USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h742zi.rs b/embassy-stm32/src/chip/stm32h742zi.rs new file mode 100644 index 00000000..16c6b22f --- /dev/null +++ b/embassy-stm32/src/chip/stm32h742zi.rs @@ -0,0 +1,892 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPUART1, + MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, SAI4, SDMMC1, + SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, USART1, + USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h743ag.rs b/embassy-stm32/src/chip/stm32h743ag.rs new file mode 100644 index 00000000..061955f8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h743ag.rs @@ -0,0 +1,901 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h743ai.rs b/embassy-stm32/src/chip/stm32h743ai.rs new file mode 100644 index 00000000..061955f8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h743ai.rs @@ -0,0 +1,901 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h743bg.rs b/embassy-stm32/src/chip/stm32h743bg.rs new file mode 100644 index 00000000..061955f8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h743bg.rs @@ -0,0 +1,901 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h743bi.rs b/embassy-stm32/src/chip/stm32h743bi.rs new file mode 100644 index 00000000..061955f8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h743bi.rs @@ -0,0 +1,901 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h743ig.rs b/embassy-stm32/src/chip/stm32h743ig.rs new file mode 100644 index 00000000..061955f8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h743ig.rs @@ -0,0 +1,901 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h743ii.rs b/embassy-stm32/src/chip/stm32h743ii.rs new file mode 100644 index 00000000..061955f8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h743ii.rs @@ -0,0 +1,901 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h743vg.rs b/embassy-stm32/src/chip/stm32h743vg.rs new file mode 100644 index 00000000..d7d3d60e --- /dev/null +++ b/embassy-stm32/src/chip/stm32h743vg.rs @@ -0,0 +1,901 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, + TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, + USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h743vi.rs b/embassy-stm32/src/chip/stm32h743vi.rs new file mode 100644 index 00000000..d7d3d60e --- /dev/null +++ b/embassy-stm32/src/chip/stm32h743vi.rs @@ -0,0 +1,901 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, + TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, + USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h743xg.rs b/embassy-stm32/src/chip/stm32h743xg.rs new file mode 100644 index 00000000..061955f8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h743xg.rs @@ -0,0 +1,901 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h743xi.rs b/embassy-stm32/src/chip/stm32h743xi.rs new file mode 100644 index 00000000..061955f8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h743xi.rs @@ -0,0 +1,901 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h743zg.rs b/embassy-stm32/src/chip/stm32h743zg.rs new file mode 100644 index 00000000..061955f8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h743zg.rs @@ -0,0 +1,901 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h743zi.rs b/embassy-stm32/src/chip/stm32h743zi.rs new file mode 100644 index 00000000..061955f8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h743zi.rs @@ -0,0 +1,901 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h745bg.rs b/embassy-stm32/src/chip/stm32h745bg.rs new file mode 100644 index 00000000..c6f4316a --- /dev/null +++ b/embassy-stm32/src/chip/stm32h745bg.rs @@ -0,0 +1,915 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h745bi.rs b/embassy-stm32/src/chip/stm32h745bi.rs new file mode 100644 index 00000000..c6f4316a --- /dev/null +++ b/embassy-stm32/src/chip/stm32h745bi.rs @@ -0,0 +1,915 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h745ig.rs b/embassy-stm32/src/chip/stm32h745ig.rs new file mode 100644 index 00000000..c6f4316a --- /dev/null +++ b/embassy-stm32/src/chip/stm32h745ig.rs @@ -0,0 +1,915 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h745ii.rs b/embassy-stm32/src/chip/stm32h745ii.rs new file mode 100644 index 00000000..c6f4316a --- /dev/null +++ b/embassy-stm32/src/chip/stm32h745ii.rs @@ -0,0 +1,915 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h745xg.rs b/embassy-stm32/src/chip/stm32h745xg.rs new file mode 100644 index 00000000..c6f4316a --- /dev/null +++ b/embassy-stm32/src/chip/stm32h745xg.rs @@ -0,0 +1,915 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h745xi.rs b/embassy-stm32/src/chip/stm32h745xi.rs new file mode 100644 index 00000000..c6f4316a --- /dev/null +++ b/embassy-stm32/src/chip/stm32h745xi.rs @@ -0,0 +1,915 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h745zg.rs b/embassy-stm32/src/chip/stm32h745zg.rs new file mode 100644 index 00000000..c6f4316a --- /dev/null +++ b/embassy-stm32/src/chip/stm32h745zg.rs @@ -0,0 +1,915 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h745zi.rs b/embassy-stm32/src/chip/stm32h745zi.rs new file mode 100644 index 00000000..c6f4316a --- /dev/null +++ b/embassy-stm32/src/chip/stm32h745zi.rs @@ -0,0 +1,915 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h747ag.rs b/embassy-stm32/src/chip/stm32h747ag.rs new file mode 100644 index 00000000..48827a95 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h747ag.rs @@ -0,0 +1,918 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h747ai.rs b/embassy-stm32/src/chip/stm32h747ai.rs new file mode 100644 index 00000000..48827a95 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h747ai.rs @@ -0,0 +1,918 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h747bg.rs b/embassy-stm32/src/chip/stm32h747bg.rs new file mode 100644 index 00000000..48827a95 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h747bg.rs @@ -0,0 +1,918 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h747bi.rs b/embassy-stm32/src/chip/stm32h747bi.rs new file mode 100644 index 00000000..48827a95 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h747bi.rs @@ -0,0 +1,918 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h747ig.rs b/embassy-stm32/src/chip/stm32h747ig.rs new file mode 100644 index 00000000..48827a95 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h747ig.rs @@ -0,0 +1,918 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h747ii.rs b/embassy-stm32/src/chip/stm32h747ii.rs new file mode 100644 index 00000000..48827a95 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h747ii.rs @@ -0,0 +1,918 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h747xg.rs b/embassy-stm32/src/chip/stm32h747xg.rs new file mode 100644 index 00000000..48827a95 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h747xg.rs @@ -0,0 +1,918 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h747xi.rs b/embassy-stm32/src/chip/stm32h747xi.rs new file mode 100644 index 00000000..48827a95 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h747xi.rs @@ -0,0 +1,918 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h747zi.rs b/embassy-stm32/src/chip/stm32h747zi.rs new file mode 100644 index 00000000..8c3a0f51 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h747zi.rs @@ -0,0 +1,918 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, DAC1, DCMI, DMA2D, ETH, FDCAN1, + FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, + PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, + PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, + PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, + PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, + LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SAI3, + SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, + TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, + USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h750ib.rs b/embassy-stm32/src/chip/stm32h750ib.rs new file mode 100644 index 00000000..7f0e79d8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h750ib.rs @@ -0,0 +1,904 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CRYP, DAC1, DCMI, DMA2D, ETH, + FDCAN1, FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, + PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, + PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, + PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, + PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, + PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, + PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, + PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, + PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, + LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, + SAI3, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, + TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, + UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h750vb.rs b/embassy-stm32/src/chip/stm32h750vb.rs new file mode 100644 index 00000000..6d8a74d8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h750vb.rs @@ -0,0 +1,904 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CRYP, DAC1, DCMI, DMA2D, ETH, + FDCAN1, FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, + PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, + PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, + PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, + PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, + PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, + PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, + PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, + PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, + LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, + SAI3, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h750xb.rs b/embassy-stm32/src/chip/stm32h750xb.rs new file mode 100644 index 00000000..7f0e79d8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h750xb.rs @@ -0,0 +1,904 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CRYP, DAC1, DCMI, DMA2D, ETH, + FDCAN1, FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, + PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, + PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, + PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, + PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, + PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, + PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, + PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, + PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, + LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, + SAI3, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, + TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, + UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h750zb.rs b/embassy-stm32/src/chip/stm32h750zb.rs new file mode 100644 index 00000000..7f0e79d8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h750zb.rs @@ -0,0 +1,904 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CRYP, DAC1, DCMI, DMA2D, ETH, + FDCAN1, FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, + PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, + PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, + PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, + PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, + PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, + PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, + PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, + PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, + LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, + SAI3, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, + TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, + UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h753ai.rs b/embassy-stm32/src/chip/stm32h753ai.rs new file mode 100644 index 00000000..7f0e79d8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h753ai.rs @@ -0,0 +1,904 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CRYP, DAC1, DCMI, DMA2D, ETH, + FDCAN1, FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, + PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, + PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, + PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, + PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, + PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, + PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, + PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, + PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, + LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, + SAI3, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, + TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, + UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h753bi.rs b/embassy-stm32/src/chip/stm32h753bi.rs new file mode 100644 index 00000000..7f0e79d8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h753bi.rs @@ -0,0 +1,904 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CRYP, DAC1, DCMI, DMA2D, ETH, + FDCAN1, FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, + PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, + PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, + PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, + PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, + PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, + PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, + PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, + PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, + LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, + SAI3, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, + TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, + UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h753ii.rs b/embassy-stm32/src/chip/stm32h753ii.rs new file mode 100644 index 00000000..7f0e79d8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h753ii.rs @@ -0,0 +1,904 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CRYP, DAC1, DCMI, DMA2D, ETH, + FDCAN1, FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, + PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, + PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, + PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, + PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, + PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, + PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, + PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, + PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, + LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, + SAI3, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, + TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, + UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h753vi.rs b/embassy-stm32/src/chip/stm32h753vi.rs new file mode 100644 index 00000000..6d8a74d8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h753vi.rs @@ -0,0 +1,904 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CRYP, DAC1, DCMI, DMA2D, ETH, + FDCAN1, FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, + PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, + PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, + PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, + PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, + PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, + PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, + PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, + PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, + LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, + SAI3, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, + TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, + UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h753xi.rs b/embassy-stm32/src/chip/stm32h753xi.rs new file mode 100644 index 00000000..7f0e79d8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h753xi.rs @@ -0,0 +1,904 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CRYP, DAC1, DCMI, DMA2D, ETH, + FDCAN1, FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, + PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, + PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, + PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, + PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, + PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, + PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, + PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, + PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, + LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, + SAI3, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, + TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, + UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h753zi.rs b/embassy-stm32/src/chip/stm32h753zi.rs new file mode 100644 index 00000000..7f0e79d8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h753zi.rs @@ -0,0 +1,904 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CRYP, DAC1, DCMI, DMA2D, ETH, + FDCAN1, FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, + PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, + PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, + PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, + PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, + PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, + PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, + PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, + PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPTIM4, + LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, + SAI3, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, + TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, + UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h755bi.rs b/embassy-stm32/src/chip/stm32h755bi.rs new file mode 100644 index 00000000..225ca3f5 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h755bi.rs @@ -0,0 +1,919 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CRYP, DAC1, DCMI, DMA2D, ETH, + FDCAN1, FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, + PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, + PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, + PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, + PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, + PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, + PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, + PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, + PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, + LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, + SAI2, SAI3, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, + TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, + UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, + WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h755ii.rs b/embassy-stm32/src/chip/stm32h755ii.rs new file mode 100644 index 00000000..225ca3f5 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h755ii.rs @@ -0,0 +1,919 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CRYP, DAC1, DCMI, DMA2D, ETH, + FDCAN1, FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, + PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, + PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, + PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, + PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, + PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, + PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, + PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, + PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, + LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, + SAI2, SAI3, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, + TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, + UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, + WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h755xi.rs b/embassy-stm32/src/chip/stm32h755xi.rs new file mode 100644 index 00000000..225ca3f5 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h755xi.rs @@ -0,0 +1,919 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CRYP, DAC1, DCMI, DMA2D, ETH, + FDCAN1, FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, + PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, + PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, + PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, + PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, + PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, + PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, + PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, + PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, + LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, + SAI2, SAI3, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, + TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, + UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, + WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h755zi.rs b/embassy-stm32/src/chip/stm32h755zi.rs new file mode 100644 index 00000000..225ca3f5 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h755zi.rs @@ -0,0 +1,919 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CRYP, DAC1, DCMI, DMA2D, ETH, + FDCAN1, FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, + PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, + PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, + PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, + PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, + PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, + PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, + PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, + PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, + LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, + SAI2, SAI3, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, + TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, + UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, + WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h757ai.rs b/embassy-stm32/src/chip/stm32h757ai.rs new file mode 100644 index 00000000..90d611be --- /dev/null +++ b/embassy-stm32/src/chip/stm32h757ai.rs @@ -0,0 +1,922 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CRYP, DAC1, DCMI, DMA2D, ETH, + FDCAN1, FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, + PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, + PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, + PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, + PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, + PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, + PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, + PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, + PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, + LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, + SAI2, SAI3, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, + TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, + UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, + WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h757bi.rs b/embassy-stm32/src/chip/stm32h757bi.rs new file mode 100644 index 00000000..90d611be --- /dev/null +++ b/embassy-stm32/src/chip/stm32h757bi.rs @@ -0,0 +1,922 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CRYP, DAC1, DCMI, DMA2D, ETH, + FDCAN1, FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, + PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, + PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, + PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, + PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, + PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, + PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, + PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, + PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, + LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, + SAI2, SAI3, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, + TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, + UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, + WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h757ii.rs b/embassy-stm32/src/chip/stm32h757ii.rs new file mode 100644 index 00000000..90d611be --- /dev/null +++ b/embassy-stm32/src/chip/stm32h757ii.rs @@ -0,0 +1,922 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CRYP, DAC1, DCMI, DMA2D, ETH, + FDCAN1, FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, + PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, + PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, + PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, + PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, + PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, + PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, + PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, + PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, + LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, + SAI2, SAI3, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, + TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, + UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, + WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h757xi.rs b/embassy-stm32/src/chip/stm32h757xi.rs new file mode 100644 index 00000000..90d611be --- /dev/null +++ b/embassy-stm32/src/chip/stm32h757xi.rs @@ -0,0 +1,922 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CRYP, DAC1, DCMI, DMA2D, ETH, + FDCAN1, FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, + PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, + PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, + PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, + PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, + PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, + PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, + PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, + PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, + LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, + SAI2, SAI3, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, TIM1, + TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, + UART5, UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, + WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h757zi.rs b/embassy-stm32/src/chip/stm32h757zi.rs new file mode 100644 index 00000000..3bc83c70 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h757zi.rs @@ -0,0 +1,921 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, BDMA, COMP1, COMP2, CRYP, DAC1, DCMI, DMA2D, ETH, + FDCAN1, FDCAN2, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, + PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, + PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, + PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, + PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, + PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, + PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, + PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, + PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, IWDG2, JPEG, LPTIM1, LPTIM2, LPTIM3, + LPTIM4, LPTIM5, LPUART1, LTDC, MDIOS, MDMA, OPAMP1, OPAMP2, PWR, QUADSPI, RCC, RNG, RTC, SAI1, + SAI2, SAI3, SAI4, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, SPI4, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, + TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, + UART7, UART8, USART1, USART2, USART3, USART6, USB_OTG_FS, USB_OTG_HS, VREFBUF, WWDG1, WWDG2 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); diff --git a/embassy-stm32/src/chip/stm32h7a3ag.rs b/embassy-stm32/src/chip/stm32h7a3ag.rs new file mode 100644 index 00000000..9496672f --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7a3ag.rs @@ -0,0 +1,886 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, COMP2, DAC1, DAC2, DCMI, DMA2D, DTS, + FDCAN1, FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, + LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, + TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, + UART4, UART5, UART7, UART8, UART9, USART1, USART10, USART2, USART3, USART6, USB_OTG_HS, + VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7a3ai.rs b/embassy-stm32/src/chip/stm32h7a3ai.rs new file mode 100644 index 00000000..9496672f --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7a3ai.rs @@ -0,0 +1,886 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, COMP2, DAC1, DAC2, DCMI, DMA2D, DTS, + FDCAN1, FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, + LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, + TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, + UART4, UART5, UART7, UART8, UART9, USART1, USART10, USART2, USART3, USART6, USB_OTG_HS, + VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7a3ig.rs b/embassy-stm32/src/chip/stm32h7a3ig.rs new file mode 100644 index 00000000..9496672f --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7a3ig.rs @@ -0,0 +1,886 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, COMP2, DAC1, DAC2, DCMI, DMA2D, DTS, + FDCAN1, FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, + LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, + TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, + UART4, UART5, UART7, UART8, UART9, USART1, USART10, USART2, USART3, USART6, USB_OTG_HS, + VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7a3ii.rs b/embassy-stm32/src/chip/stm32h7a3ii.rs new file mode 100644 index 00000000..9496672f --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7a3ii.rs @@ -0,0 +1,886 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, COMP2, DAC1, DAC2, DCMI, DMA2D, DTS, + FDCAN1, FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, + LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, + TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, + UART4, UART5, UART7, UART8, UART9, USART1, USART10, USART2, USART3, USART6, USB_OTG_HS, + VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7a3lg.rs b/embassy-stm32/src/chip/stm32h7a3lg.rs new file mode 100644 index 00000000..9496672f --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7a3lg.rs @@ -0,0 +1,886 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, COMP2, DAC1, DAC2, DCMI, DMA2D, DTS, + FDCAN1, FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, + LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, + TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, + UART4, UART5, UART7, UART8, UART9, USART1, USART10, USART2, USART3, USART6, USB_OTG_HS, + VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7a3li.rs b/embassy-stm32/src/chip/stm32h7a3li.rs new file mode 100644 index 00000000..9496672f --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7a3li.rs @@ -0,0 +1,886 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, COMP2, DAC1, DAC2, DCMI, DMA2D, DTS, + FDCAN1, FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, + LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, + TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, + UART4, UART5, UART7, UART8, UART9, USART1, USART10, USART2, USART3, USART6, USB_OTG_HS, + VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7a3ng.rs b/embassy-stm32/src/chip/stm32h7a3ng.rs new file mode 100644 index 00000000..9496672f --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7a3ng.rs @@ -0,0 +1,886 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, COMP2, DAC1, DAC2, DCMI, DMA2D, DTS, + FDCAN1, FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, + LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, + TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, + UART4, UART5, UART7, UART8, UART9, USART1, USART10, USART2, USART3, USART6, USB_OTG_HS, + VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7a3ni.rs b/embassy-stm32/src/chip/stm32h7a3ni.rs new file mode 100644 index 00000000..9496672f --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7a3ni.rs @@ -0,0 +1,886 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, COMP2, DAC1, DAC2, DCMI, DMA2D, DTS, + FDCAN1, FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, + LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, + TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, + UART4, UART5, UART7, UART8, UART9, USART1, USART10, USART2, USART3, USART6, USB_OTG_HS, + VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7a3qi.rs b/embassy-stm32/src/chip/stm32h7a3qi.rs new file mode 100644 index 00000000..0a1a11d7 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7a3qi.rs @@ -0,0 +1,886 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, COMP2, DAC1, DAC2, DCMI, DMA2D, DTS, + FDCAN1, FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, + LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI4, SPI6, SWPMI1, SYSCFG, TIM1, + TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, + UART5, UART7, UART8, UART9, USART1, USART10, USART2, USART3, USART6, USB_OTG_HS, VREFBUF, + WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7a3rg.rs b/embassy-stm32/src/chip/stm32h7a3rg.rs new file mode 100644 index 00000000..b9a317e4 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7a3rg.rs @@ -0,0 +1,885 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, DAC1, DAC2, DMA2D, DTS, FDCAN1, + FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, + PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, + PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, + PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, + PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, + PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, + PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, + PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, + PK13, PK14, PK15, I2C1, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPUART1, LTDC, MDIOS, + MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, PWR, RCC, RNG, RTC, SAI2, SDMMC1, SDMMC2, SPDIFRX, + SPI1, SPI2, SPI3, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, + TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, USART1, USART2, USART3, USART6, + USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7a3ri.rs b/embassy-stm32/src/chip/stm32h7a3ri.rs new file mode 100644 index 00000000..b9a317e4 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7a3ri.rs @@ -0,0 +1,885 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, DAC1, DAC2, DMA2D, DTS, FDCAN1, + FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, + PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, + PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, + PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, + PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, + PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, + PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, + PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, + PK13, PK14, PK15, I2C1, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPUART1, LTDC, MDIOS, + MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, PWR, RCC, RNG, RTC, SAI2, SDMMC1, SDMMC2, SPDIFRX, + SPI1, SPI2, SPI3, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, + TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, USART1, USART2, USART3, USART6, + USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7a3vg.rs b/embassy-stm32/src/chip/stm32h7a3vg.rs new file mode 100644 index 00000000..0a1a11d7 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7a3vg.rs @@ -0,0 +1,886 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, COMP2, DAC1, DAC2, DCMI, DMA2D, DTS, + FDCAN1, FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, + LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI4, SPI6, SWPMI1, SYSCFG, TIM1, + TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, + UART5, UART7, UART8, UART9, USART1, USART10, USART2, USART3, USART6, USB_OTG_HS, VREFBUF, + WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7a3vi.rs b/embassy-stm32/src/chip/stm32h7a3vi.rs new file mode 100644 index 00000000..0a1a11d7 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7a3vi.rs @@ -0,0 +1,886 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, COMP2, DAC1, DAC2, DCMI, DMA2D, DTS, + FDCAN1, FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, + LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI4, SPI6, SWPMI1, SYSCFG, TIM1, + TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, + UART5, UART7, UART8, UART9, USART1, USART10, USART2, USART3, USART6, USB_OTG_HS, VREFBUF, + WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7a3zg.rs b/embassy-stm32/src/chip/stm32h7a3zg.rs new file mode 100644 index 00000000..9496672f --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7a3zg.rs @@ -0,0 +1,886 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, COMP2, DAC1, DAC2, DCMI, DMA2D, DTS, + FDCAN1, FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, + LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, + TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, + UART4, UART5, UART7, UART8, UART9, USART1, USART10, USART2, USART3, USART6, USB_OTG_HS, + VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7a3zi.rs b/embassy-stm32/src/chip/stm32h7a3zi.rs new file mode 100644 index 00000000..9496672f --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7a3zi.rs @@ -0,0 +1,886 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, COMP2, DAC1, DAC2, DCMI, DMA2D, DTS, + FDCAN1, FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, + LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PSSI, PWR, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SWPMI1, SYSCFG, + TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, + UART4, UART5, UART7, UART8, UART9, USART1, USART10, USART2, USART3, USART6, USB_OTG_HS, + VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7b0ab.rs b/embassy-stm32/src/chip/stm32h7b0ab.rs new file mode 100644 index 00000000..279f688d --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7b0ab.rs @@ -0,0 +1,895 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, COMP2, CRYP, DAC1, DAC2, DCMI, DMA2D, + DTS, FDCAN1, FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, + PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, + PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, + PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, + PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, + PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, + PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, + PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, + PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, + LPTIM3, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, OTFDEC1, + OTFDEC2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI4, + SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, + TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, UART9, USART1, USART10, USART2, USART3, + USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7b0ib.rs b/embassy-stm32/src/chip/stm32h7b0ib.rs new file mode 100644 index 00000000..279f688d --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7b0ib.rs @@ -0,0 +1,895 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, COMP2, CRYP, DAC1, DAC2, DCMI, DMA2D, + DTS, FDCAN1, FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, + PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, + PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, + PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, + PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, + PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, + PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, + PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, + PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, + LPTIM3, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, OTFDEC1, + OTFDEC2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI4, + SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, + TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, UART9, USART1, USART10, USART2, USART3, + USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7b0rb.rs b/embassy-stm32/src/chip/stm32h7b0rb.rs new file mode 100644 index 00000000..2e945c3a --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7b0rb.rs @@ -0,0 +1,894 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, CRYP, DAC1, DAC2, DMA2D, DTS, FDCAN1, + FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, + PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, + PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, + PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, + PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, + PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, + PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, + PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, + PK13, PK14, PK15, HASH, I2C1, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPUART1, LTDC, + MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OTFDEC1, PWR, RCC, RNG, RTC, SAI2, SDMMC1, + SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, USART1, USART2, + USART3, USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7b0vb.rs b/embassy-stm32/src/chip/stm32h7b0vb.rs new file mode 100644 index 00000000..f283be64 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7b0vb.rs @@ -0,0 +1,895 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, COMP2, CRYP, DAC1, DAC2, DCMI, DMA2D, + DTS, FDCAN1, FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, + PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, + PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, + PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, + PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, + PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, + PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, + PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, + PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, + LPTIM3, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, OTFDEC1, + PSSI, PWR, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI4, SPI6, + SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, + TIM7, TIM8, UART4, UART5, UART7, UART8, UART9, USART1, USART10, USART2, USART3, USART6, + USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7b0zb.rs b/embassy-stm32/src/chip/stm32h7b0zb.rs new file mode 100644 index 00000000..279f688d --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7b0zb.rs @@ -0,0 +1,895 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, COMP2, CRYP, DAC1, DAC2, DCMI, DMA2D, + DTS, FDCAN1, FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, + PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, + PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, + PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, + PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, + PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, + PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, + PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, + PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, + LPTIM3, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, OTFDEC1, + OTFDEC2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI4, + SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, + TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, UART9, USART1, USART10, USART2, USART3, + USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7b3ai.rs b/embassy-stm32/src/chip/stm32h7b3ai.rs new file mode 100644 index 00000000..279f688d --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7b3ai.rs @@ -0,0 +1,895 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, COMP2, CRYP, DAC1, DAC2, DCMI, DMA2D, + DTS, FDCAN1, FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, + PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, + PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, + PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, + PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, + PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, + PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, + PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, + PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, + LPTIM3, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, OTFDEC1, + OTFDEC2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI4, + SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, + TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, UART9, USART1, USART10, USART2, USART3, + USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7b3ii.rs b/embassy-stm32/src/chip/stm32h7b3ii.rs new file mode 100644 index 00000000..279f688d --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7b3ii.rs @@ -0,0 +1,895 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, COMP2, CRYP, DAC1, DAC2, DCMI, DMA2D, + DTS, FDCAN1, FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, + PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, + PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, + PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, + PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, + PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, + PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, + PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, + PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, + LPTIM3, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, OTFDEC1, + OTFDEC2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI4, + SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, + TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, UART9, USART1, USART10, USART2, USART3, + USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7b3li.rs b/embassy-stm32/src/chip/stm32h7b3li.rs new file mode 100644 index 00000000..279f688d --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7b3li.rs @@ -0,0 +1,895 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, COMP2, CRYP, DAC1, DAC2, DCMI, DMA2D, + DTS, FDCAN1, FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, + PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, + PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, + PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, + PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, + PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, + PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, + PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, + PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, + LPTIM3, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, OTFDEC1, + OTFDEC2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI4, + SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, + TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, UART9, USART1, USART10, USART2, USART3, + USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7b3ni.rs b/embassy-stm32/src/chip/stm32h7b3ni.rs new file mode 100644 index 00000000..279f688d --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7b3ni.rs @@ -0,0 +1,895 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, COMP2, CRYP, DAC1, DAC2, DCMI, DMA2D, + DTS, FDCAN1, FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, + PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, + PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, + PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, + PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, + PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, + PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, + PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, + PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, + LPTIM3, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, OTFDEC1, + OTFDEC2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI4, + SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, + TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, UART9, USART1, USART10, USART2, USART3, + USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7b3qi.rs b/embassy-stm32/src/chip/stm32h7b3qi.rs new file mode 100644 index 00000000..f283be64 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7b3qi.rs @@ -0,0 +1,895 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, COMP2, CRYP, DAC1, DAC2, DCMI, DMA2D, + DTS, FDCAN1, FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, + PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, + PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, + PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, + PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, + PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, + PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, + PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, + PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, + LPTIM3, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, OTFDEC1, + PSSI, PWR, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI4, SPI6, + SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, + TIM7, TIM8, UART4, UART5, UART7, UART8, UART9, USART1, USART10, USART2, USART3, USART6, + USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7b3ri.rs b/embassy-stm32/src/chip/stm32h7b3ri.rs new file mode 100644 index 00000000..2e945c3a --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7b3ri.rs @@ -0,0 +1,894 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, CRYP, DAC1, DAC2, DMA2D, DTS, FDCAN1, + FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, + PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, + PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, + PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, + PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, + PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, + PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, + PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, + PK13, PK14, PK15, HASH, I2C1, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, LPTIM3, LPUART1, LTDC, + MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OTFDEC1, PWR, RCC, RNG, RTC, SAI2, SDMMC1, + SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, USART1, USART2, + USART3, USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7b3vi.rs b/embassy-stm32/src/chip/stm32h7b3vi.rs new file mode 100644 index 00000000..f283be64 --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7b3vi.rs @@ -0,0 +1,895 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, COMP2, CRYP, DAC1, DAC2, DCMI, DMA2D, + DTS, FDCAN1, FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, + PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, + PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, + PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, + PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, + PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, + PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, + PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, + PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, + LPTIM3, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, OTFDEC1, + PSSI, PWR, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI4, SPI6, + SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, + TIM7, TIM8, UART4, UART5, UART7, UART8, UART9, USART1, USART10, USART2, USART3, USART6, + USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32h7b3zi.rs b/embassy-stm32/src/chip/stm32h7b3zi.rs new file mode 100644 index 00000000..279f688d --- /dev/null +++ b/embassy-stm32/src/chip/stm32h7b3zi.rs @@ -0,0 +1,895 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, BDMA1, BDMA2, COMP1, COMP2, CRYP, DAC1, DAC2, DCMI, DMA2D, + DTS, FDCAN1, FDCAN2, GFXMMU, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, + PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, + PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, + PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, + PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, + PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, + PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, + PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, + PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG1, JPEG, LPTIM1, LPTIM2, + LPTIM3, LPUART1, LTDC, MDIOS, MDMA, OCTOSPI1, OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, OTFDEC1, + OTFDEC2, PSSI, PWR, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPDIFRX, SPI1, SPI2, SPI3, SPI4, + SPI5, SPI6, SWPMI1, SYSCFG, TIM1, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, + TIM5, TIM6, TIM7, TIM8, UART4, UART5, UART7, UART8, UART9, USART1, USART10, USART2, USART3, + USART6, USB_OTG_HS, VREFBUF, WWDG1 +); +pub const GPIO_BASE: usize = 0x58020000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +impl_rng!(0x48021800); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); diff --git a/embassy-stm32/src/chip/stm32l412c8.rs b/embassy-stm32/src/chip/stm32l412c8.rs new file mode 100644 index 00000000..bac694b4 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l412c8.rs @@ -0,0 +1,415 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, + PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, + PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, + PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, + PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, + SPI1, SPI2, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USART3, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l412cb.rs b/embassy-stm32/src/chip/stm32l412cb.rs new file mode 100644 index 00000000..bac694b4 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l412cb.rs @@ -0,0 +1,415 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, + PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, + PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, + PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, + PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, + SPI1, SPI2, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USART3, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l412k8.rs b/embassy-stm32/src/chip/stm32l412k8.rs new file mode 100644 index 00000000..ca012748 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l412k8.rs @@ -0,0 +1,415 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, + PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, + PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, + PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, + PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, SPI1, + SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l412kb.rs b/embassy-stm32/src/chip/stm32l412kb.rs new file mode 100644 index 00000000..ca012748 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l412kb.rs @@ -0,0 +1,415 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, + PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, + PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, + PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, + PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, SPI1, + SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l412r8.rs b/embassy-stm32/src/chip/stm32l412r8.rs new file mode 100644 index 00000000..bac694b4 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l412r8.rs @@ -0,0 +1,415 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, + PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, + PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, + PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, + PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, + SPI1, SPI2, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USART3, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l412rb.rs b/embassy-stm32/src/chip/stm32l412rb.rs new file mode 100644 index 00000000..bac694b4 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l412rb.rs @@ -0,0 +1,415 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, + PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, + PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, + PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, + PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, + SPI1, SPI2, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USART3, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l412t8.rs b/embassy-stm32/src/chip/stm32l412t8.rs new file mode 100644 index 00000000..ca012748 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l412t8.rs @@ -0,0 +1,415 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, + PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, + PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, + PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, + PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, SPI1, + SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l412tb.rs b/embassy-stm32/src/chip/stm32l412tb.rs new file mode 100644 index 00000000..ca012748 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l412tb.rs @@ -0,0 +1,415 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, COMP1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, + PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, + PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, + PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, + PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, SPI1, + SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l422cb.rs b/embassy-stm32/src/chip/stm32l422cb.rs new file mode 100644 index 00000000..a6023e5e --- /dev/null +++ b/embassy-stm32/src/chip/stm32l422cb.rs @@ -0,0 +1,419 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, COMP1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, + PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, + RTC, SPI1, SPI2, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USART3, USB, + WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l422kb.rs b/embassy-stm32/src/chip/stm32l422kb.rs new file mode 100644 index 00000000..4d13988a --- /dev/null +++ b/embassy-stm32/src/chip/stm32l422kb.rs @@ -0,0 +1,418 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, COMP1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, + PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, + SPI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l422rb.rs b/embassy-stm32/src/chip/stm32l422rb.rs new file mode 100644 index 00000000..a6023e5e --- /dev/null +++ b/embassy-stm32/src/chip/stm32l422rb.rs @@ -0,0 +1,419 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, COMP1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, + PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, + RTC, SPI1, SPI2, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USART3, USB, + WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l422tb.rs b/embassy-stm32/src/chip/stm32l422tb.rs new file mode 100644 index 00000000..4d13988a --- /dev/null +++ b/embassy-stm32/src/chip/stm32l422tb.rs @@ -0,0 +1,418 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, COMP1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, + PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, + SPI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TSC, USART1, USART2, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l431cb.rs b/embassy-stm32/src/chip/stm32l431cb.rs new file mode 100644 index 00000000..a0d5c2f0 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l431cb.rs @@ -0,0 +1,457 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, + PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, + SAI1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1, + USART2, USART3, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l431cc.rs b/embassy-stm32/src/chip/stm32l431cc.rs new file mode 100644 index 00000000..a0d5c2f0 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l431cc.rs @@ -0,0 +1,457 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, + PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, + SAI1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1, + USART2, USART3, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l431kb.rs b/embassy-stm32/src/chip/stm32l431kb.rs new file mode 100644 index 00000000..4835b504 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l431kb.rs @@ -0,0 +1,456 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, + PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, SAI1, + SPI1, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1, USART2, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l431kc.rs b/embassy-stm32/src/chip/stm32l431kc.rs new file mode 100644 index 00000000..4835b504 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l431kc.rs @@ -0,0 +1,456 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, + PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, SAI1, + SPI1, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1, USART2, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l431rb.rs b/embassy-stm32/src/chip/stm32l431rb.rs new file mode 100644 index 00000000..40229c74 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l431rb.rs @@ -0,0 +1,457 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, + PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, + SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, + USART1, USART2, USART3, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l431rc.rs b/embassy-stm32/src/chip/stm32l431rc.rs new file mode 100644 index 00000000..40229c74 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l431rc.rs @@ -0,0 +1,457 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, + PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, + SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, + USART1, USART2, USART3, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l431vc.rs b/embassy-stm32/src/chip/stm32l431vc.rs new file mode 100644 index 00000000..40229c74 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l431vc.rs @@ -0,0 +1,457 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, + PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, RTC, + SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, + USART1, USART2, USART3, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l432kb.rs b/embassy-stm32/src/chip/stm32l432kb.rs new file mode 100644 index 00000000..5fb08a73 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l432kb.rs @@ -0,0 +1,411 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, + RTC, SAI1, SPI1, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1, + USART2, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SPI1 = 35, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SPI1); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SPI1(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI1 }, + Vector { _reserved: 0 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l432kc.rs b/embassy-stm32/src/chip/stm32l432kc.rs new file mode 100644 index 00000000..5fb08a73 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l432kc.rs @@ -0,0 +1,411 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, + RTC, SAI1, SPI1, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1, + USART2, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SPI1 = 35, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SPI1); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SPI1(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI1 }, + Vector { _reserved: 0 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l433cb.rs b/embassy-stm32/src/chip/stm32l433cb.rs new file mode 100644 index 00000000..4e18e5f2 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l433cb.rs @@ -0,0 +1,463 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, + PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, + RTC, SAI1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1, + USART2, USART3, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l433cc.rs b/embassy-stm32/src/chip/stm32l433cc.rs new file mode 100644 index 00000000..4e18e5f2 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l433cc.rs @@ -0,0 +1,463 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, + PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, + RTC, SAI1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1, + USART2, USART3, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l433rb.rs b/embassy-stm32/src/chip/stm32l433rb.rs new file mode 100644 index 00000000..c6e6c1cd --- /dev/null +++ b/embassy-stm32/src/chip/stm32l433rb.rs @@ -0,0 +1,463 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, + PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, + RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, + USART1, USART2, USART3, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l433rc.rs b/embassy-stm32/src/chip/stm32l433rc.rs new file mode 100644 index 00000000..c6e6c1cd --- /dev/null +++ b/embassy-stm32/src/chip/stm32l433rc.rs @@ -0,0 +1,463 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, + PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, + RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, + USART1, USART2, USART3, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l433vc.rs b/embassy-stm32/src/chip/stm32l433vc.rs new file mode 100644 index 00000000..c6e6c1cd --- /dev/null +++ b/embassy-stm32/src/chip/stm32l433vc.rs @@ -0,0 +1,463 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, + PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, + RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, + USART1, USART2, USART3, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l442kc.rs b/embassy-stm32/src/chip/stm32l442kc.rs new file mode 100644 index 00000000..b3360d12 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l442kc.rs @@ -0,0 +1,414 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, + PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, + PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, + PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, + PH11, PH12, PH13, PH14, PH15, I2C1, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, + RNG, RTC, SAI1, SPI1, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, USART1, + USART2, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SPI1 = 35, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SPI1); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SPI1(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI1 }, + Vector { _reserved: 0 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l443cc.rs b/embassy-stm32/src/chip/stm32l443cc.rs new file mode 100644 index 00000000..cc9fa363 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l443cc.rs @@ -0,0 +1,466 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, + PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, + PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, + PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, + PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, + PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, + RNG, RTC, SAI1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, TSC, + USART1, USART2, USART3, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l443rc.rs b/embassy-stm32/src/chip/stm32l443rc.rs new file mode 100644 index 00000000..b0cf88ca --- /dev/null +++ b/embassy-stm32/src/chip/stm32l443rc.rs @@ -0,0 +1,466 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, + PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, + PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, + PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, + PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, + PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, + RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, + TSC, USART1, USART2, USART3, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l443vc.rs b/embassy-stm32/src/chip/stm32l443vc.rs new file mode 100644 index 00000000..b0cf88ca --- /dev/null +++ b/embassy-stm32/src/chip/stm32l443vc.rs @@ -0,0 +1,466 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, + PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, + PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, + PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, + PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, + PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, + RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM6, TIM7, + TSC, USART1, USART2, USART3, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l451cc.rs b/embassy-stm32/src/chip/stm32l451cc.rs new file mode 100644 index 00000000..803f18cc --- /dev/null +++ b/embassy-stm32/src/chip/stm32l451cc.rs @@ -0,0 +1,475 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, + PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, + RTC, SAI1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4, USART1, + USART2, USART3, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l451ce.rs b/embassy-stm32/src/chip/stm32l451ce.rs new file mode 100644 index 00000000..803f18cc --- /dev/null +++ b/embassy-stm32/src/chip/stm32l451ce.rs @@ -0,0 +1,475 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, + PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, + RTC, SAI1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4, USART1, + USART2, USART3, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l451rc.rs b/embassy-stm32/src/chip/stm32l451rc.rs new file mode 100644 index 00000000..0cbd5d0c --- /dev/null +++ b/embassy-stm32/src/chip/stm32l451rc.rs @@ -0,0 +1,475 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, + PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, + RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4, + USART1, USART2, USART3, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l451re.rs b/embassy-stm32/src/chip/stm32l451re.rs new file mode 100644 index 00000000..0cbd5d0c --- /dev/null +++ b/embassy-stm32/src/chip/stm32l451re.rs @@ -0,0 +1,475 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, + PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, + RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4, + USART1, USART2, USART3, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l451vc.rs b/embassy-stm32/src/chip/stm32l451vc.rs new file mode 100644 index 00000000..0cbd5d0c --- /dev/null +++ b/embassy-stm32/src/chip/stm32l451vc.rs @@ -0,0 +1,475 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, + PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, + RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4, + USART1, USART2, USART3, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l451ve.rs b/embassy-stm32/src/chip/stm32l451ve.rs new file mode 100644 index 00000000..0cbd5d0c --- /dev/null +++ b/embassy-stm32/src/chip/stm32l451ve.rs @@ -0,0 +1,475 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, + PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, + RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4, + USART1, USART2, USART3, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l452cc.rs b/embassy-stm32/src/chip/stm32l452cc.rs new file mode 100644 index 00000000..8e24b096 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l452cc.rs @@ -0,0 +1,478 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, + PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, + RTC, SAI1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4, USART1, + USART2, USART3, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l452ce.rs b/embassy-stm32/src/chip/stm32l452ce.rs new file mode 100644 index 00000000..8e24b096 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l452ce.rs @@ -0,0 +1,478 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, + PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, + RTC, SAI1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4, USART1, + USART2, USART3, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l452rc.rs b/embassy-stm32/src/chip/stm32l452rc.rs new file mode 100644 index 00000000..d5387b34 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l452rc.rs @@ -0,0 +1,478 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, + PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, + RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4, + USART1, USART2, USART3, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l452re.rs b/embassy-stm32/src/chip/stm32l452re.rs new file mode 100644 index 00000000..d5387b34 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l452re.rs @@ -0,0 +1,478 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, + PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, + RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4, + USART1, USART2, USART3, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l452vc.rs b/embassy-stm32/src/chip/stm32l452vc.rs new file mode 100644 index 00000000..d5387b34 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l452vc.rs @@ -0,0 +1,478 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, + PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, + RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4, + USART1, USART2, USART3, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l452ve.rs b/embassy-stm32/src/chip/stm32l452ve.rs new file mode 100644 index 00000000..d5387b34 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l452ve.rs @@ -0,0 +1,478 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, + PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, + PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, + PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, + PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, RNG, + RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4, + USART1, USART2, USART3, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l462ce.rs b/embassy-stm32/src/chip/stm32l462ce.rs new file mode 100644 index 00000000..98710177 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l462ce.rs @@ -0,0 +1,481 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, + PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, + PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, + PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, + PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, + PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, + RNG, RTC, SAI1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, UART4, + USART1, USART2, USART3, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l462re.rs b/embassy-stm32/src/chip/stm32l462re.rs new file mode 100644 index 00000000..fbf4b119 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l462re.rs @@ -0,0 +1,481 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, + PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, + PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, + PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, + PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, + PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, + RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, + UART4, USART1, USART2, USART3, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l462ve.rs b/embassy-stm32/src/chip/stm32l462ve.rs new file mode 100644 index 00000000..fbf4b119 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l462ve.rs @@ -0,0 +1,481 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, PA5, PA6, + PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, + PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, + PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, + PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, + PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, QUADSPI, RCC, + RNG, RTC, SAI1, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM2, TIM3, TIM6, TSC, + UART4, USART1, USART2, USART3, USB, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l471qe.rs b/embassy-stm32/src/chip/stm32l471qe.rs new file mode 100644 index 00000000..c2ed491d --- /dev/null +++ b/embassy-stm32/src/chip/stm32l471qe.rs @@ -0,0 +1,545 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, + TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l471qg.rs b/embassy-stm32/src/chip/stm32l471qg.rs new file mode 100644 index 00000000..c2ed491d --- /dev/null +++ b/embassy-stm32/src/chip/stm32l471qg.rs @@ -0,0 +1,545 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, + TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l471re.rs b/embassy-stm32/src/chip/stm32l471re.rs new file mode 100644 index 00000000..c2ed491d --- /dev/null +++ b/embassy-stm32/src/chip/stm32l471re.rs @@ -0,0 +1,545 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, + TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l471rg.rs b/embassy-stm32/src/chip/stm32l471rg.rs new file mode 100644 index 00000000..c2ed491d --- /dev/null +++ b/embassy-stm32/src/chip/stm32l471rg.rs @@ -0,0 +1,545 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, + TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l471ve.rs b/embassy-stm32/src/chip/stm32l471ve.rs new file mode 100644 index 00000000..c2ed491d --- /dev/null +++ b/embassy-stm32/src/chip/stm32l471ve.rs @@ -0,0 +1,545 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, + TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l471vg.rs b/embassy-stm32/src/chip/stm32l471vg.rs new file mode 100644 index 00000000..c2ed491d --- /dev/null +++ b/embassy-stm32/src/chip/stm32l471vg.rs @@ -0,0 +1,545 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, + TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l471ze.rs b/embassy-stm32/src/chip/stm32l471ze.rs new file mode 100644 index 00000000..c2ed491d --- /dev/null +++ b/embassy-stm32/src/chip/stm32l471ze.rs @@ -0,0 +1,545 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, + TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l471zg.rs b/embassy-stm32/src/chip/stm32l471zg.rs new file mode 100644 index 00000000..c2ed491d --- /dev/null +++ b/embassy-stm32/src/chip/stm32l471zg.rs @@ -0,0 +1,545 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, + TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l475rc.rs b/embassy-stm32/src/chip/stm32l475rc.rs new file mode 100644 index 00000000..8c33d13d --- /dev/null +++ b/embassy-stm32/src/chip/stm32l475rc.rs @@ -0,0 +1,549 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, + TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, + WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l475re.rs b/embassy-stm32/src/chip/stm32l475re.rs new file mode 100644 index 00000000..8c33d13d --- /dev/null +++ b/embassy-stm32/src/chip/stm32l475re.rs @@ -0,0 +1,549 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, + TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, + WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l475rg.rs b/embassy-stm32/src/chip/stm32l475rg.rs new file mode 100644 index 00000000..8c33d13d --- /dev/null +++ b/embassy-stm32/src/chip/stm32l475rg.rs @@ -0,0 +1,549 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, + TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, + WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l475vc.rs b/embassy-stm32/src/chip/stm32l475vc.rs new file mode 100644 index 00000000..8c33d13d --- /dev/null +++ b/embassy-stm32/src/chip/stm32l475vc.rs @@ -0,0 +1,549 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, + TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, + WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l475ve.rs b/embassy-stm32/src/chip/stm32l475ve.rs new file mode 100644 index 00000000..8c33d13d --- /dev/null +++ b/embassy-stm32/src/chip/stm32l475ve.rs @@ -0,0 +1,549 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, + TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, + WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l475vg.rs b/embassy-stm32/src/chip/stm32l475vg.rs new file mode 100644 index 00000000..8c33d13d --- /dev/null +++ b/embassy-stm32/src/chip/stm32l475vg.rs @@ -0,0 +1,549 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, + TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, + WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476je.rs b/embassy-stm32/src/chip/stm32l476je.rs new file mode 100644 index 00000000..8e468038 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l476je.rs @@ -0,0 +1,552 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, + RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, + TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, + USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476jg.rs b/embassy-stm32/src/chip/stm32l476jg.rs new file mode 100644 index 00000000..8e468038 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l476jg.rs @@ -0,0 +1,552 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, + RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, + TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, + USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476me.rs b/embassy-stm32/src/chip/stm32l476me.rs new file mode 100644 index 00000000..8e468038 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l476me.rs @@ -0,0 +1,552 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, + RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, + TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, + USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476mg.rs b/embassy-stm32/src/chip/stm32l476mg.rs new file mode 100644 index 00000000..8e468038 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l476mg.rs @@ -0,0 +1,552 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, + RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, + TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, + USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476qe.rs b/embassy-stm32/src/chip/stm32l476qe.rs new file mode 100644 index 00000000..8e468038 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l476qe.rs @@ -0,0 +1,552 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, + RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, + TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, + USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476qg.rs b/embassy-stm32/src/chip/stm32l476qg.rs new file mode 100644 index 00000000..8e468038 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l476qg.rs @@ -0,0 +1,552 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, + RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, + TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, + USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476rc.rs b/embassy-stm32/src/chip/stm32l476rc.rs new file mode 100644 index 00000000..8e468038 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l476rc.rs @@ -0,0 +1,552 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, + RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, + TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, + USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476re.rs b/embassy-stm32/src/chip/stm32l476re.rs new file mode 100644 index 00000000..8e468038 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l476re.rs @@ -0,0 +1,552 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, + RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, + TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, + USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476rg.rs b/embassy-stm32/src/chip/stm32l476rg.rs new file mode 100644 index 00000000..8e468038 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l476rg.rs @@ -0,0 +1,552 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, + RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, + TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, + USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476vc.rs b/embassy-stm32/src/chip/stm32l476vc.rs new file mode 100644 index 00000000..8e468038 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l476vc.rs @@ -0,0 +1,552 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, + RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, + TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, + USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476ve.rs b/embassy-stm32/src/chip/stm32l476ve.rs new file mode 100644 index 00000000..8e468038 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l476ve.rs @@ -0,0 +1,552 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, + RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, + TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, + USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476vg.rs b/embassy-stm32/src/chip/stm32l476vg.rs new file mode 100644 index 00000000..8e468038 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l476vg.rs @@ -0,0 +1,552 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, + RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, + TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, + USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476ze.rs b/embassy-stm32/src/chip/stm32l476ze.rs new file mode 100644 index 00000000..8e468038 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l476ze.rs @@ -0,0 +1,552 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, + RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, + TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, + USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l476zg.rs b/embassy-stm32/src/chip/stm32l476zg.rs new file mode 100644 index 00000000..8e468038 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l476zg.rs @@ -0,0 +1,552 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, + RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, + TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, + USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l485jc.rs b/embassy-stm32/src/chip/stm32l485jc.rs new file mode 100644 index 00000000..6172b0d5 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l485jc.rs @@ -0,0 +1,552 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, + PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, + PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, + TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, + WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l485je.rs b/embassy-stm32/src/chip/stm32l485je.rs new file mode 100644 index 00000000..6172b0d5 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l485je.rs @@ -0,0 +1,552 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, + PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, + PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, RNG, + RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, + TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, + WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l486jg.rs b/embassy-stm32/src/chip/stm32l486jg.rs new file mode 100644 index 00000000..84a63dc8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l486jg.rs @@ -0,0 +1,555 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, + PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, + PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, + RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, + TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, + USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l486qg.rs b/embassy-stm32/src/chip/stm32l486qg.rs new file mode 100644 index 00000000..84a63dc8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l486qg.rs @@ -0,0 +1,555 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, + PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, + PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, + RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, + TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, + USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l486rg.rs b/embassy-stm32/src/chip/stm32l486rg.rs new file mode 100644 index 00000000..84a63dc8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l486rg.rs @@ -0,0 +1,555 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, + PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, + PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, + RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, + TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, + USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l486vg.rs b/embassy-stm32/src/chip/stm32l486vg.rs new file mode 100644 index 00000000..84a63dc8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l486vg.rs @@ -0,0 +1,555 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, + PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, + PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, + RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, + TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, + USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l486zg.rs b/embassy-stm32/src/chip/stm32l486zg.rs new file mode 100644 index 00000000..84a63dc8 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l486zg.rs @@ -0,0 +1,555 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, COMP1, COMP2, DAC1, PA0, PA1, PA2, PA3, + PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, + PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, I2C1, I2C2, I2C3, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, QUADSPI, RCC, + RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, TIM16, TIM17, + TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, USART3, + USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l496ae.rs b/embassy-stm32/src/chip/stm32l496ae.rs new file mode 100644 index 00000000..bb4ecfae --- /dev/null +++ b/embassy-stm32/src/chip/stm32l496ae.rs @@ -0,0 +1,605 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, + PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, + PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, + PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, + PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, + PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, + QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, + USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l496ag.rs b/embassy-stm32/src/chip/stm32l496ag.rs new file mode 100644 index 00000000..bb4ecfae --- /dev/null +++ b/embassy-stm32/src/chip/stm32l496ag.rs @@ -0,0 +1,605 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, + PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, + PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, + PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, + PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, + PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, + QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, + USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l496qe.rs b/embassy-stm32/src/chip/stm32l496qe.rs new file mode 100644 index 00000000..bb4ecfae --- /dev/null +++ b/embassy-stm32/src/chip/stm32l496qe.rs @@ -0,0 +1,605 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, + PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, + PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, + PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, + PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, + PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, + QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, + USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l496qg.rs b/embassy-stm32/src/chip/stm32l496qg.rs new file mode 100644 index 00000000..bb4ecfae --- /dev/null +++ b/embassy-stm32/src/chip/stm32l496qg.rs @@ -0,0 +1,605 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, + PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, + PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, + PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, + PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, + PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, + QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, + USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l496re.rs b/embassy-stm32/src/chip/stm32l496re.rs new file mode 100644 index 00000000..bb4ecfae --- /dev/null +++ b/embassy-stm32/src/chip/stm32l496re.rs @@ -0,0 +1,605 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, + PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, + PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, + PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, + PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, + PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, + QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, + USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l496rg.rs b/embassy-stm32/src/chip/stm32l496rg.rs new file mode 100644 index 00000000..bb4ecfae --- /dev/null +++ b/embassy-stm32/src/chip/stm32l496rg.rs @@ -0,0 +1,605 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, + PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, + PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, + PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, + PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, + PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, + QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, + USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l496ve.rs b/embassy-stm32/src/chip/stm32l496ve.rs new file mode 100644 index 00000000..bb4ecfae --- /dev/null +++ b/embassy-stm32/src/chip/stm32l496ve.rs @@ -0,0 +1,605 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, + PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, + PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, + PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, + PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, + PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, + QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, + USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l496vg.rs b/embassy-stm32/src/chip/stm32l496vg.rs new file mode 100644 index 00000000..bb4ecfae --- /dev/null +++ b/embassy-stm32/src/chip/stm32l496vg.rs @@ -0,0 +1,605 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, + PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, + PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, + PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, + PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, + PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, + QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, + USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l496wg.rs b/embassy-stm32/src/chip/stm32l496wg.rs new file mode 100644 index 00000000..bb4ecfae --- /dev/null +++ b/embassy-stm32/src/chip/stm32l496wg.rs @@ -0,0 +1,605 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, + PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, + PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, + PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, + PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, + PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, + QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, + USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l496ze.rs b/embassy-stm32/src/chip/stm32l496ze.rs new file mode 100644 index 00000000..bb4ecfae --- /dev/null +++ b/embassy-stm32/src/chip/stm32l496ze.rs @@ -0,0 +1,605 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, + PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, + PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, + PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, + PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, + PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, + QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, + USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l496zg.rs b/embassy-stm32/src/chip/stm32l496zg.rs new file mode 100644 index 00000000..bb4ecfae --- /dev/null +++ b/embassy-stm32/src/chip/stm32l496zg.rs @@ -0,0 +1,605 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, + PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, + PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, + PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, + PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, + PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, OPAMP2, + QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, + USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4a6ag.rs b/embassy-stm32/src/chip/stm32l4a6ag.rs new file mode 100644 index 00000000..e4bc4756 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4a6ag.rs @@ -0,0 +1,608 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, + OPAMP2, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, + TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, + USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4a6qg.rs b/embassy-stm32/src/chip/stm32l4a6qg.rs new file mode 100644 index 00000000..e4bc4756 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4a6qg.rs @@ -0,0 +1,608 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, + OPAMP2, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, + TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, + USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4a6rg.rs b/embassy-stm32/src/chip/stm32l4a6rg.rs new file mode 100644 index 00000000..e4bc4756 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4a6rg.rs @@ -0,0 +1,608 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, + OPAMP2, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, + TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, + USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4a6vg.rs b/embassy-stm32/src/chip/stm32l4a6vg.rs new file mode 100644 index 00000000..e4bc4756 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4a6vg.rs @@ -0,0 +1,608 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, + OPAMP2, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, + TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, + USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4a6zg.rs b/embassy-stm32/src/chip/stm32l4a6zg.rs new file mode 100644 index 00000000..e4bc4756 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4a6zg.rs @@ -0,0 +1,608 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, ADC3, AES, CAN1, CAN2, COMP1, COMP2, DAC1, DCMI, DMA2D, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LCD, LPTIM1, LPTIM2, LPUART1, OPAMP1, + OPAMP2, QUADSPI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SWPMI1, SYSCFG, TIM1, + TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, + USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4p5ae.rs b/embassy-stm32/src/chip/stm32l4p5ae.rs new file mode 100644 index 00000000..e2867eca --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4p5ae.rs @@ -0,0 +1,597 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, + PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, + PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, + SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, + USART1, USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4p5ag.rs b/embassy-stm32/src/chip/stm32l4p5ag.rs new file mode 100644 index 00000000..e2867eca --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4p5ag.rs @@ -0,0 +1,597 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, + PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, + PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, + SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, + USART1, USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4p5ce.rs b/embassy-stm32/src/chip/stm32l4p5ce.rs new file mode 100644 index 00000000..f2e7c308 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4p5ce.rs @@ -0,0 +1,597 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DMA2D, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC2, SPI1, SPI2, SPI3, SYSCFG, TIM1, + TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, USART1, USART2, + USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4p5cg.rs b/embassy-stm32/src/chip/stm32l4p5cg.rs new file mode 100644 index 00000000..f2e7c308 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4p5cg.rs @@ -0,0 +1,597 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DMA2D, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC2, SPI1, SPI2, SPI3, SYSCFG, TIM1, + TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, USART1, USART2, + USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4p5qe.rs b/embassy-stm32/src/chip/stm32l4p5qe.rs new file mode 100644 index 00000000..e2867eca --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4p5qe.rs @@ -0,0 +1,597 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, + PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, + PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, + SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, + USART1, USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4p5qg.rs b/embassy-stm32/src/chip/stm32l4p5qg.rs new file mode 100644 index 00000000..e2867eca --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4p5qg.rs @@ -0,0 +1,597 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, + PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, + PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, + SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, + USART1, USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4p5re.rs b/embassy-stm32/src/chip/stm32l4p5re.rs new file mode 100644 index 00000000..9b27401b --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4p5re.rs @@ -0,0 +1,597 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, + PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, + PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, + SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, + USART1, USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4p5rg.rs b/embassy-stm32/src/chip/stm32l4p5rg.rs new file mode 100644 index 00000000..9b27401b --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4p5rg.rs @@ -0,0 +1,597 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, + PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, + PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, + SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, + USART1, USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4p5ve.rs b/embassy-stm32/src/chip/stm32l4p5ve.rs new file mode 100644 index 00000000..e2867eca --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4p5ve.rs @@ -0,0 +1,597 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, + PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, + PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, + SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, + USART1, USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4p5vg.rs b/embassy-stm32/src/chip/stm32l4p5vg.rs new file mode 100644 index 00000000..e2867eca --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4p5vg.rs @@ -0,0 +1,597 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, + PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, + PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, + SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, + USART1, USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4p5ze.rs b/embassy-stm32/src/chip/stm32l4p5ze.rs new file mode 100644 index 00000000..e2867eca --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4p5ze.rs @@ -0,0 +1,597 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, + PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, + PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, + SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, + USART1, USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4p5zg.rs b/embassy-stm32/src/chip/stm32l4p5zg.rs new file mode 100644 index 00000000..e2867eca --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4p5zg.rs @@ -0,0 +1,597 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, + PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, + PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, SPI2, SPI3, + SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, + USART1, USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4q5ag.rs b/embassy-stm32/src/chip/stm32l4q5ag.rs new file mode 100644 index 00000000..9bc33dee --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4q5ag.rs @@ -0,0 +1,603 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, + PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, + PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, + PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, + PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, + PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, + PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, + PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, + PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, + OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PKA, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, + SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, + UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PKA = 86, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PKA); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PKA(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: PKA }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4q5cg.rs b/embassy-stm32/src/chip/stm32l4q5cg.rs new file mode 100644 index 00000000..b5d3cfc4 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4q5cg.rs @@ -0,0 +1,603 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, CAN1, COMP1, COMP2, DAC1, DMA2D, PA0, PA1, PA2, PA3, + PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, + PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, PKA, RCC, RNG, RTC, SAI1, SAI2, SDMMC2, SPI1, SPI2, SPI3, SYSCFG, + TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, USART1, + USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PKA = 86, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PKA); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PKA(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: PKA }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4q5qg.rs b/embassy-stm32/src/chip/stm32l4q5qg.rs new file mode 100644 index 00000000..9bc33dee --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4q5qg.rs @@ -0,0 +1,603 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, + PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, + PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, + PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, + PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, + PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, + PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, + PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, + PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, + OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PKA, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, + SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, + UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PKA = 86, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PKA); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PKA(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: PKA }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4q5rg.rs b/embassy-stm32/src/chip/stm32l4q5rg.rs new file mode 100644 index 00000000..6f532676 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4q5rg.rs @@ -0,0 +1,603 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, + PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, + PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, + PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, + PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, + PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, + PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, + PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, + PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, + OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PKA, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, + SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, + UART4, USART1, USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PKA = 86, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PKA); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PKA(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: PKA }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4q5vg.rs b/embassy-stm32/src/chip/stm32l4q5vg.rs new file mode 100644 index 00000000..9bc33dee --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4q5vg.rs @@ -0,0 +1,603 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, + PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, + PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, + PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, + PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, + PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, + PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, + PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, + PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, + OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PKA, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, + SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, + UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PKA = 86, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PKA); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PKA(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: PKA }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4q5zg.rs b/embassy-stm32/src/chip/stm32l4q5zg.rs new file mode 100644 index 00000000..9bc33dee --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4q5zg.rs @@ -0,0 +1,603 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, ADC2, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, + PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, + PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, + PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, + PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, + PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, + PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, + PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, + PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, + OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, PKA, PSSI, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SDMMC2, SPI1, + SPI2, SPI3, SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, + UART4, UART5, USART1, USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PKA = 86, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PKA); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PKA(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: PKA }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r5ag.rs b/embassy-stm32/src/chip/stm32l4r5ag.rs new file mode 100644 index 00000000..d3300817 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4r5ag.rs @@ -0,0 +1,596 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2, OCTOSPIM, + OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, + USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r5ai.rs b/embassy-stm32/src/chip/stm32l4r5ai.rs new file mode 100644 index 00000000..d3300817 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4r5ai.rs @@ -0,0 +1,596 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2, OCTOSPIM, + OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, + USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r5qg.rs b/embassy-stm32/src/chip/stm32l4r5qg.rs new file mode 100644 index 00000000..d3300817 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4r5qg.rs @@ -0,0 +1,596 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2, OCTOSPIM, + OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, + USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r5qi.rs b/embassy-stm32/src/chip/stm32l4r5qi.rs new file mode 100644 index 00000000..d3300817 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4r5qi.rs @@ -0,0 +1,596 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2, OCTOSPIM, + OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, + USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r5vg.rs b/embassy-stm32/src/chip/stm32l4r5vg.rs new file mode 100644 index 00000000..d3300817 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4r5vg.rs @@ -0,0 +1,596 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2, OCTOSPIM, + OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, + USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r5vi.rs b/embassy-stm32/src/chip/stm32l4r5vi.rs new file mode 100644 index 00000000..d3300817 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4r5vi.rs @@ -0,0 +1,596 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2, OCTOSPIM, + OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, + USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r5zg.rs b/embassy-stm32/src/chip/stm32l4r5zg.rs new file mode 100644 index 00000000..d3300817 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4r5zg.rs @@ -0,0 +1,596 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2, OCTOSPIM, + OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, + USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r5zi.rs b/embassy-stm32/src/chip/stm32l4r5zi.rs new file mode 100644 index 00000000..d3300817 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4r5zi.rs @@ -0,0 +1,596 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, PA4, + PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, + PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, + PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2, OCTOSPIM, + OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, TIM15, + TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, USART2, + USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r7ai.rs b/embassy-stm32/src/chip/stm32l4r7ai.rs new file mode 100644 index 00000000..bdb3be97 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4r7ai.rs @@ -0,0 +1,605 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1, PA2, + PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, + PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, + PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, + PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, + PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, + PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, + PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, + PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, + TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, + USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r7vi.rs b/embassy-stm32/src/chip/stm32l4r7vi.rs new file mode 100644 index 00000000..bdb3be97 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4r7vi.rs @@ -0,0 +1,605 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1, PA2, + PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, + PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, + PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, + PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, + PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, + PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, + PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, + PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, + TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, + USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r7zi.rs b/embassy-stm32/src/chip/stm32l4r7zi.rs new file mode 100644 index 00000000..bdb3be97 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4r7zi.rs @@ -0,0 +1,605 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1, PA2, + PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, + PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, + PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, + PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, + PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, + PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, + PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, + PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, + TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, + USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r9ag.rs b/embassy-stm32/src/chip/stm32l4r9ag.rs new file mode 100644 index 00000000..d04c323b --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4r9ag.rs @@ -0,0 +1,608 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1, PA2, + PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, + PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, + PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, + PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, + PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, + PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, + PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, + PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, + TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, + USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r9ai.rs b/embassy-stm32/src/chip/stm32l4r9ai.rs new file mode 100644 index 00000000..d04c323b --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4r9ai.rs @@ -0,0 +1,608 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1, PA2, + PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, + PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, + PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, + PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, + PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, + PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, + PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, + PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, + TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, + USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r9vg.rs b/embassy-stm32/src/chip/stm32l4r9vg.rs new file mode 100644 index 00000000..d04c323b --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4r9vg.rs @@ -0,0 +1,608 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1, PA2, + PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, + PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, + PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, + PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, + PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, + PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, + PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, + PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, + TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, + USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r9vi.rs b/embassy-stm32/src/chip/stm32l4r9vi.rs new file mode 100644 index 00000000..d04c323b --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4r9vi.rs @@ -0,0 +1,608 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1, PA2, + PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, + PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, + PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, + PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, + PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, + PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, + PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, + PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, + TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, + USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r9zg.rs b/embassy-stm32/src/chip/stm32l4r9zg.rs new file mode 100644 index 00000000..d04c323b --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4r9zg.rs @@ -0,0 +1,608 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1, PA2, + PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, + PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, + PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, + PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, + PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, + PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, + PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, + PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, + TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, + USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4r9zi.rs b/embassy-stm32/src/chip/stm32l4r9zi.rs new file mode 100644 index 00000000..d04c323b --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4r9zi.rs @@ -0,0 +1,608 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1, PA2, + PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, + PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, + PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, + PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, + PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, + PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, + PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, + PI14, PI15, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, + TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, + USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4s5ai.rs b/embassy-stm32/src/chip/stm32l4s5ai.rs new file mode 100644 index 00000000..502294f2 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4s5ai.rs @@ -0,0 +1,599 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, + PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, + PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, + TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, + USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4s5qi.rs b/embassy-stm32/src/chip/stm32l4s5qi.rs new file mode 100644 index 00000000..502294f2 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4s5qi.rs @@ -0,0 +1,599 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, + PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, + PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, + TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, + USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4s5vi.rs b/embassy-stm32/src/chip/stm32l4s5vi.rs new file mode 100644 index 00000000..502294f2 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4s5vi.rs @@ -0,0 +1,599 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, + PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, + PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, + TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, + USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4s5zi.rs b/embassy-stm32/src/chip/stm32l4s5zi.rs new file mode 100644 index 00000000..502294f2 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4s5zi.rs @@ -0,0 +1,599 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, PA0, PA1, PA2, PA3, + PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, + PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, + PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, + PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, + PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, + PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, + PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, + PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, OCTOSPI1, OCTOSPI2, + OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, SYSCFG, TIM1, + TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, USART1, + USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4s7ai.rs b/embassy-stm32/src/chip/stm32l4s7ai.rs new file mode 100644 index 00000000..502c2789 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4s7ai.rs @@ -0,0 +1,608 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1, + PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, + PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, + PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, + PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, + PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, + PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, + PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, + PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, + OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, + SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, + USART1, USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4s7vi.rs b/embassy-stm32/src/chip/stm32l4s7vi.rs new file mode 100644 index 00000000..502c2789 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4s7vi.rs @@ -0,0 +1,608 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1, + PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, + PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, + PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, + PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, + PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, + PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, + PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, + PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, + OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, + SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, + USART1, USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4s7zi.rs b/embassy-stm32/src/chip/stm32l4s7zi.rs new file mode 100644 index 00000000..502c2789 --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4s7zi.rs @@ -0,0 +1,608 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1, + PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, + PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, + PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, + PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, + PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, + PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, + PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, + PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, + OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, + SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, + USART1, USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4s9ai.rs b/embassy-stm32/src/chip/stm32l4s9ai.rs new file mode 100644 index 00000000..e2f7294c --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4s9ai.rs @@ -0,0 +1,611 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1, + PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, + PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, + PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, + PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, + PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, + PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, + PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, + PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, + OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, + SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, + USART1, USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4s9vi.rs b/embassy-stm32/src/chip/stm32l4s9vi.rs new file mode 100644 index 00000000..e2f7294c --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4s9vi.rs @@ -0,0 +1,611 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1, + PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, + PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, + PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, + PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, + PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, + PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, + PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, + PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, + OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, + SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, + USART1, USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/chip/stm32l4s9zi.rs b/embassy-stm32/src/chip/stm32l4s9zi.rs new file mode 100644 index 00000000..e2f7294c --- /dev/null +++ b/embassy-stm32/src/chip/stm32l4s9zi.rs @@ -0,0 +1,611 @@ +use embassy_extras::peripherals; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, ADC1, AES, CAN1, COMP1, COMP2, DAC1, DCMI, DMA2D, GFXMMU, PA0, PA1, + PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3, + PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, + PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, + PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, + PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, + PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, + PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, + PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, + PI14, PI15, HASH, I2C1, I2C2, I2C3, I2C4, IWDG, LPTIM1, LPTIM2, LPUART1, LTDC, OCTOSPI1, + OCTOSPI2, OCTOSPIM, OPAMP1, OPAMP2, RCC, RNG, RTC, SAI1, SAI2, SDMMC1, SPI1, SPI2, SPI3, + SYSCFG, TIM1, TIM15, TIM16, TIM17, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8, TSC, UART4, UART5, + USART1, USART2, USART3, USB_OTG_FS, WWDG +); +pub const GPIO_BASE: usize = 0x48000000; +pub const GPIO_STRIDE: usize = 0x400; + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_rng!(0x50060800); diff --git a/embassy-stm32/src/h7/mod.rs b/embassy-stm32/src/h7/mod.rs new file mode 100644 index 00000000..9dcd3d3e --- /dev/null +++ b/embassy-stm32/src/h7/mod.rs @@ -0,0 +1 @@ +pub mod rcc; diff --git a/embassy-stm32/src/h7/rcc.rs b/embassy-stm32/src/h7/rcc.rs new file mode 100644 index 00000000..7affaf57 --- /dev/null +++ b/embassy-stm32/src/h7/rcc.rs @@ -0,0 +1,36 @@ +use crate::time::Hertz; + +/// Frozen core clock frequencies +#[derive(Clone, Copy)] +pub struct CoreClocks { + pub hclk: Hertz, + pub pclk1: Hertz, + pub pclk2: Hertz, + pub pclk3: Hertz, + pub pclk4: Hertz, + pub ppre1: u8, + pub ppre2: u8, + pub ppre3: u8, + pub ppre4: u8, + pub csi_ck: Option, + pub hsi_ck: Option, + pub hsi48_ck: Option, + pub lsi_ck: Option, + pub per_ck: Option, + pub hse_ck: Option, + pub mco1_ck: Option, + pub mco2_ck: Option, + pub pll1_p_ck: Option, + pub pll1_q_ck: Option, + pub pll1_r_ck: Option, + pub pll2_p_ck: Option, + pub pll2_q_ck: Option, + pub pll2_r_ck: Option, + pub pll3_p_ck: Option, + pub pll3_q_ck: Option, + pub pll3_r_ck: Option, + pub timx_ker_ck: Hertz, + pub timy_ker_ck: Hertz, + pub sys_ck: Hertz, + pub c_ck: Hertz, +} diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs index 82a73938..97d41f10 100644 --- a/embassy-stm32/src/lib.rs +++ b/embassy-stm32/src/lib.rs @@ -22,6 +22,19 @@ pub mod spi; #[cfg(feature = "_usart")] pub mod usart; +#[macro_use] +pub mod sdmmc_v2; + +#[cfg(feature = "_sdmmc_v2")] +pub use sdmmc_v2 as sdmmc; + +pub mod time; + +#[cfg(feature = "stm32h750vb")] +mod h7; +#[cfg(feature = "stm32h750vb")] +pub use h7::rcc; + // This must go LAST so that it sees the `impl_foo!` macros mod pac; pub mod time; diff --git a/embassy-stm32/src/pac/mod.rs b/embassy-stm32/src/pac/mod.rs index 35fff08c..2dfd2962 100644 --- a/embassy-stm32/src/pac/mod.rs +++ b/embassy-stm32/src/pac/mod.rs @@ -147,6 +147,119 @@ #[cfg_attr(feature = "stm32f479vi", path = "stm32f479vi.rs")] #[cfg_attr(feature = "stm32f479zg", path = "stm32f479zg.rs")] #[cfg_attr(feature = "stm32f479zi", path = "stm32f479zi.rs")] +#[cfg_attr(feature = "stm32h723ve", path = "stm32h723ve.rs")] +#[cfg_attr(feature = "stm32h723vg", path = "stm32h723vg.rs")] +#[cfg_attr(feature = "stm32h723ze", path = "stm32h723ze.rs")] +#[cfg_attr(feature = "stm32h723zg", path = "stm32h723zg.rs")] +#[cfg_attr(feature = "stm32h725ae", path = "stm32h725ae.rs")] +#[cfg_attr(feature = "stm32h725ag", path = "stm32h725ag.rs")] +#[cfg_attr(feature = "stm32h725ie", path = "stm32h725ie.rs")] +#[cfg_attr(feature = "stm32h725ig", path = "stm32h725ig.rs")] +#[cfg_attr(feature = "stm32h725re", path = "stm32h725re.rs")] +#[cfg_attr(feature = "stm32h725rg", path = "stm32h725rg.rs")] +#[cfg_attr(feature = "stm32h725ve", path = "stm32h725ve.rs")] +#[cfg_attr(feature = "stm32h725vg", path = "stm32h725vg.rs")] +#[cfg_attr(feature = "stm32h725ze", path = "stm32h725ze.rs")] +#[cfg_attr(feature = "stm32h725zg", path = "stm32h725zg.rs")] +#[cfg_attr(feature = "stm32h730ab", path = "stm32h730ab.rs")] +#[cfg_attr(feature = "stm32h730ib", path = "stm32h730ib.rs")] +#[cfg_attr(feature = "stm32h730vb", path = "stm32h730vb.rs")] +#[cfg_attr(feature = "stm32h730zb", path = "stm32h730zb.rs")] +#[cfg_attr(feature = "stm32h733vg", path = "stm32h733vg.rs")] +#[cfg_attr(feature = "stm32h733zg", path = "stm32h733zg.rs")] +#[cfg_attr(feature = "stm32h735ag", path = "stm32h735ag.rs")] +#[cfg_attr(feature = "stm32h735ig", path = "stm32h735ig.rs")] +#[cfg_attr(feature = "stm32h735rg", path = "stm32h735rg.rs")] +#[cfg_attr(feature = "stm32h735vg", path = "stm32h735vg.rs")] +#[cfg_attr(feature = "stm32h735zg", path = "stm32h735zg.rs")] +#[cfg_attr(feature = "stm32h742ag", path = "stm32h742ag.rs")] +#[cfg_attr(feature = "stm32h742ai", path = "stm32h742ai.rs")] +#[cfg_attr(feature = "stm32h742bg", path = "stm32h742bg.rs")] +#[cfg_attr(feature = "stm32h742bi", path = "stm32h742bi.rs")] +#[cfg_attr(feature = "stm32h742ig", path = "stm32h742ig.rs")] +#[cfg_attr(feature = "stm32h742ii", path = "stm32h742ii.rs")] +#[cfg_attr(feature = "stm32h742vg", path = "stm32h742vg.rs")] +#[cfg_attr(feature = "stm32h742vi", path = "stm32h742vi.rs")] +#[cfg_attr(feature = "stm32h742xg", path = "stm32h742xg.rs")] +#[cfg_attr(feature = "stm32h742xi", path = "stm32h742xi.rs")] +#[cfg_attr(feature = "stm32h742zg", path = "stm32h742zg.rs")] +#[cfg_attr(feature = "stm32h742zi", path = "stm32h742zi.rs")] +#[cfg_attr(feature = "stm32h743ag", path = "stm32h743ag.rs")] +#[cfg_attr(feature = "stm32h743ai", path = "stm32h743ai.rs")] +#[cfg_attr(feature = "stm32h743bg", path = "stm32h743bg.rs")] +#[cfg_attr(feature = "stm32h743bi", path = "stm32h743bi.rs")] +#[cfg_attr(feature = "stm32h743ig", path = "stm32h743ig.rs")] +#[cfg_attr(feature = "stm32h743ii", path = "stm32h743ii.rs")] +#[cfg_attr(feature = "stm32h743vg", path = "stm32h743vg.rs")] +#[cfg_attr(feature = "stm32h743vi", path = "stm32h743vi.rs")] +#[cfg_attr(feature = "stm32h743xg", path = "stm32h743xg.rs")] +#[cfg_attr(feature = "stm32h743xi", path = "stm32h743xi.rs")] +#[cfg_attr(feature = "stm32h743zg", path = "stm32h743zg.rs")] +#[cfg_attr(feature = "stm32h743zi", path = "stm32h743zi.rs")] +#[cfg_attr(feature = "stm32h745bg", path = "stm32h745bg.rs")] +#[cfg_attr(feature = "stm32h745bi", path = "stm32h745bi.rs")] +#[cfg_attr(feature = "stm32h745ig", path = "stm32h745ig.rs")] +#[cfg_attr(feature = "stm32h745ii", path = "stm32h745ii.rs")] +#[cfg_attr(feature = "stm32h745xg", path = "stm32h745xg.rs")] +#[cfg_attr(feature = "stm32h745xi", path = "stm32h745xi.rs")] +#[cfg_attr(feature = "stm32h745zg", path = "stm32h745zg.rs")] +#[cfg_attr(feature = "stm32h745zi", path = "stm32h745zi.rs")] +#[cfg_attr(feature = "stm32h747ag", path = "stm32h747ag.rs")] +#[cfg_attr(feature = "stm32h747ai", path = "stm32h747ai.rs")] +#[cfg_attr(feature = "stm32h747bg", path = "stm32h747bg.rs")] +#[cfg_attr(feature = "stm32h747bi", path = "stm32h747bi.rs")] +#[cfg_attr(feature = "stm32h747ig", path = "stm32h747ig.rs")] +#[cfg_attr(feature = "stm32h747ii", path = "stm32h747ii.rs")] +#[cfg_attr(feature = "stm32h747xg", path = "stm32h747xg.rs")] +#[cfg_attr(feature = "stm32h747xi", path = "stm32h747xi.rs")] +#[cfg_attr(feature = "stm32h747zi", path = "stm32h747zi.rs")] +#[cfg_attr(feature = "stm32h750ib", path = "stm32h750ib.rs")] +#[cfg_attr(feature = "stm32h750vb", path = "stm32h750vb.rs")] +#[cfg_attr(feature = "stm32h750xb", path = "stm32h750xb.rs")] +#[cfg_attr(feature = "stm32h750zb", path = "stm32h750zb.rs")] +#[cfg_attr(feature = "stm32h753ai", path = "stm32h753ai.rs")] +#[cfg_attr(feature = "stm32h753bi", path = "stm32h753bi.rs")] +#[cfg_attr(feature = "stm32h753ii", path = "stm32h753ii.rs")] +#[cfg_attr(feature = "stm32h753vi", path = "stm32h753vi.rs")] +#[cfg_attr(feature = "stm32h753xi", path = "stm32h753xi.rs")] +#[cfg_attr(feature = "stm32h753zi", path = "stm32h753zi.rs")] +#[cfg_attr(feature = "stm32h755bi", path = "stm32h755bi.rs")] +#[cfg_attr(feature = "stm32h755ii", path = "stm32h755ii.rs")] +#[cfg_attr(feature = "stm32h755xi", path = "stm32h755xi.rs")] +#[cfg_attr(feature = "stm32h755zi", path = "stm32h755zi.rs")] +#[cfg_attr(feature = "stm32h757ai", path = "stm32h757ai.rs")] +#[cfg_attr(feature = "stm32h757bi", path = "stm32h757bi.rs")] +#[cfg_attr(feature = "stm32h757ii", path = "stm32h757ii.rs")] +#[cfg_attr(feature = "stm32h757xi", path = "stm32h757xi.rs")] +#[cfg_attr(feature = "stm32h757zi", path = "stm32h757zi.rs")] +#[cfg_attr(feature = "stm32h7a3ag", path = "stm32h7a3ag.rs")] +#[cfg_attr(feature = "stm32h7a3ai", path = "stm32h7a3ai.rs")] +#[cfg_attr(feature = "stm32h7a3ig", path = "stm32h7a3ig.rs")] +#[cfg_attr(feature = "stm32h7a3ii", path = "stm32h7a3ii.rs")] +#[cfg_attr(feature = "stm32h7a3lg", path = "stm32h7a3lg.rs")] +#[cfg_attr(feature = "stm32h7a3li", path = "stm32h7a3li.rs")] +#[cfg_attr(feature = "stm32h7a3ng", path = "stm32h7a3ng.rs")] +#[cfg_attr(feature = "stm32h7a3ni", path = "stm32h7a3ni.rs")] +#[cfg_attr(feature = "stm32h7a3qi", path = "stm32h7a3qi.rs")] +#[cfg_attr(feature = "stm32h7a3rg", path = "stm32h7a3rg.rs")] +#[cfg_attr(feature = "stm32h7a3ri", path = "stm32h7a3ri.rs")] +#[cfg_attr(feature = "stm32h7a3vg", path = "stm32h7a3vg.rs")] +#[cfg_attr(feature = "stm32h7a3vi", path = "stm32h7a3vi.rs")] +#[cfg_attr(feature = "stm32h7a3zg", path = "stm32h7a3zg.rs")] +#[cfg_attr(feature = "stm32h7a3zi", path = "stm32h7a3zi.rs")] +#[cfg_attr(feature = "stm32h7b0ab", path = "stm32h7b0ab.rs")] +#[cfg_attr(feature = "stm32h7b0ib", path = "stm32h7b0ib.rs")] +#[cfg_attr(feature = "stm32h7b0rb", path = "stm32h7b0rb.rs")] +#[cfg_attr(feature = "stm32h7b0vb", path = "stm32h7b0vb.rs")] +#[cfg_attr(feature = "stm32h7b0zb", path = "stm32h7b0zb.rs")] +#[cfg_attr(feature = "stm32h7b3ai", path = "stm32h7b3ai.rs")] +#[cfg_attr(feature = "stm32h7b3ii", path = "stm32h7b3ii.rs")] +#[cfg_attr(feature = "stm32h7b3li", path = "stm32h7b3li.rs")] +#[cfg_attr(feature = "stm32h7b3ni", path = "stm32h7b3ni.rs")] +#[cfg_attr(feature = "stm32h7b3qi", path = "stm32h7b3qi.rs")] +#[cfg_attr(feature = "stm32h7b3ri", path = "stm32h7b3ri.rs")] +#[cfg_attr(feature = "stm32h7b3vi", path = "stm32h7b3vi.rs")] +#[cfg_attr(feature = "stm32h7b3zi", path = "stm32h7b3zi.rs")] #[cfg_attr(feature = "stm32l412c8", path = "stm32l412c8.rs")] #[cfg_attr(feature = "stm32l412cb", path = "stm32l412cb.rs")] #[cfg_attr(feature = "stm32l412k8", path = "stm32l412k8.rs")] diff --git a/embassy-stm32/src/pac/stm32h723ve.rs b/embassy-stm32/src/pac/stm32h723ve.rs new file mode 100644 index 00000000..020adb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h723ve.rs @@ -0,0 +1,906 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h723vg.rs b/embassy-stm32/src/pac/stm32h723vg.rs new file mode 100644 index 00000000..020adb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h723vg.rs @@ -0,0 +1,906 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h723ze.rs b/embassy-stm32/src/pac/stm32h723ze.rs new file mode 100644 index 00000000..020adb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h723ze.rs @@ -0,0 +1,906 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h723zg.rs b/embassy-stm32/src/pac/stm32h723zg.rs new file mode 100644 index 00000000..020adb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h723zg.rs @@ -0,0 +1,906 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h725ae.rs b/embassy-stm32/src/pac/stm32h725ae.rs new file mode 100644 index 00000000..020adb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h725ae.rs @@ -0,0 +1,906 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h725ag.rs b/embassy-stm32/src/pac/stm32h725ag.rs new file mode 100644 index 00000000..020adb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h725ag.rs @@ -0,0 +1,906 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h725ie.rs b/embassy-stm32/src/pac/stm32h725ie.rs new file mode 100644 index 00000000..020adb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h725ie.rs @@ -0,0 +1,906 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h725ig.rs b/embassy-stm32/src/pac/stm32h725ig.rs new file mode 100644 index 00000000..020adb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h725ig.rs @@ -0,0 +1,906 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h725re.rs b/embassy-stm32/src/pac/stm32h725re.rs new file mode 100644 index 00000000..020adb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h725re.rs @@ -0,0 +1,906 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h725rg.rs b/embassy-stm32/src/pac/stm32h725rg.rs new file mode 100644 index 00000000..020adb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h725rg.rs @@ -0,0 +1,906 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h725ve.rs b/embassy-stm32/src/pac/stm32h725ve.rs new file mode 100644 index 00000000..020adb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h725ve.rs @@ -0,0 +1,906 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h725vg.rs b/embassy-stm32/src/pac/stm32h725vg.rs new file mode 100644 index 00000000..020adb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h725vg.rs @@ -0,0 +1,906 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h725ze.rs b/embassy-stm32/src/pac/stm32h725ze.rs new file mode 100644 index 00000000..020adb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h725ze.rs @@ -0,0 +1,906 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h725zg.rs b/embassy-stm32/src/pac/stm32h725zg.rs new file mode 100644 index 00000000..020adb15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h725zg.rs @@ -0,0 +1,906 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h730ab.rs b/embassy-stm32/src/pac/stm32h730ab.rs new file mode 100644 index 00000000..b9d5b3b8 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h730ab.rs @@ -0,0 +1,915 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h730ib.rs b/embassy-stm32/src/pac/stm32h730ib.rs new file mode 100644 index 00000000..b9d5b3b8 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h730ib.rs @@ -0,0 +1,915 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h730vb.rs b/embassy-stm32/src/pac/stm32h730vb.rs new file mode 100644 index 00000000..b9d5b3b8 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h730vb.rs @@ -0,0 +1,915 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h730zb.rs b/embassy-stm32/src/pac/stm32h730zb.rs new file mode 100644 index 00000000..b9d5b3b8 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h730zb.rs @@ -0,0 +1,915 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h733vg.rs b/embassy-stm32/src/pac/stm32h733vg.rs new file mode 100644 index 00000000..b9d5b3b8 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h733vg.rs @@ -0,0 +1,915 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h733zg.rs b/embassy-stm32/src/pac/stm32h733zg.rs new file mode 100644 index 00000000..b9d5b3b8 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h733zg.rs @@ -0,0 +1,915 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h735ag.rs b/embassy-stm32/src/pac/stm32h735ag.rs new file mode 100644 index 00000000..b9d5b3b8 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h735ag.rs @@ -0,0 +1,915 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h735ig.rs b/embassy-stm32/src/pac/stm32h735ig.rs new file mode 100644 index 00000000..b9d5b3b8 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h735ig.rs @@ -0,0 +1,915 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h735rg.rs b/embassy-stm32/src/pac/stm32h735rg.rs new file mode 100644 index 00000000..b9d5b3b8 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h735rg.rs @@ -0,0 +1,915 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h735vg.rs b/embassy-stm32/src/pac/stm32h735vg.rs new file mode 100644 index 00000000..b9d5b3b8 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h735vg.rs @@ -0,0 +1,915 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h735zg.rs b/embassy-stm32/src/pac/stm32h735zg.rs new file mode 100644 index 00000000..b9d5b3b8 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h735zg.rs @@ -0,0 +1,915 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, + PK10, PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h742ag.rs b/embassy-stm32/src/pac/stm32h742ag.rs new file mode 100644 index 00000000..27e08345 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h742ag.rs @@ -0,0 +1,915 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h742ai.rs b/embassy-stm32/src/pac/stm32h742ai.rs new file mode 100644 index 00000000..27e08345 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h742ai.rs @@ -0,0 +1,915 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h742bg.rs b/embassy-stm32/src/pac/stm32h742bg.rs new file mode 100644 index 00000000..27e08345 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h742bg.rs @@ -0,0 +1,915 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h742bi.rs b/embassy-stm32/src/pac/stm32h742bi.rs new file mode 100644 index 00000000..27e08345 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h742bi.rs @@ -0,0 +1,915 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h742ig.rs b/embassy-stm32/src/pac/stm32h742ig.rs new file mode 100644 index 00000000..27e08345 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h742ig.rs @@ -0,0 +1,915 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h742ii.rs b/embassy-stm32/src/pac/stm32h742ii.rs new file mode 100644 index 00000000..27e08345 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h742ii.rs @@ -0,0 +1,915 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h742vg.rs b/embassy-stm32/src/pac/stm32h742vg.rs new file mode 100644 index 00000000..27e08345 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h742vg.rs @@ -0,0 +1,915 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h742vi.rs b/embassy-stm32/src/pac/stm32h742vi.rs new file mode 100644 index 00000000..27e08345 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h742vi.rs @@ -0,0 +1,915 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h742xg.rs b/embassy-stm32/src/pac/stm32h742xg.rs new file mode 100644 index 00000000..27e08345 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h742xg.rs @@ -0,0 +1,915 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h742xi.rs b/embassy-stm32/src/pac/stm32h742xi.rs new file mode 100644 index 00000000..27e08345 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h742xi.rs @@ -0,0 +1,915 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h742zg.rs b/embassy-stm32/src/pac/stm32h742zg.rs new file mode 100644 index 00000000..27e08345 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h742zg.rs @@ -0,0 +1,915 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h742zi.rs b/embassy-stm32/src/pac/stm32h742zi.rs new file mode 100644 index 00000000..27e08345 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h742zi.rs @@ -0,0 +1,915 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h743ag.rs b/embassy-stm32/src/pac/stm32h743ag.rs new file mode 100644 index 00000000..46665ee5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h743ag.rs @@ -0,0 +1,924 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h743ai.rs b/embassy-stm32/src/pac/stm32h743ai.rs new file mode 100644 index 00000000..46665ee5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h743ai.rs @@ -0,0 +1,924 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h743bg.rs b/embassy-stm32/src/pac/stm32h743bg.rs new file mode 100644 index 00000000..46665ee5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h743bg.rs @@ -0,0 +1,924 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h743bi.rs b/embassy-stm32/src/pac/stm32h743bi.rs new file mode 100644 index 00000000..46665ee5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h743bi.rs @@ -0,0 +1,924 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h743ig.rs b/embassy-stm32/src/pac/stm32h743ig.rs new file mode 100644 index 00000000..46665ee5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h743ig.rs @@ -0,0 +1,924 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h743ii.rs b/embassy-stm32/src/pac/stm32h743ii.rs new file mode 100644 index 00000000..46665ee5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h743ii.rs @@ -0,0 +1,924 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h743vg.rs b/embassy-stm32/src/pac/stm32h743vg.rs new file mode 100644 index 00000000..46665ee5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h743vg.rs @@ -0,0 +1,924 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h743vi.rs b/embassy-stm32/src/pac/stm32h743vi.rs new file mode 100644 index 00000000..46665ee5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h743vi.rs @@ -0,0 +1,924 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h743xg.rs b/embassy-stm32/src/pac/stm32h743xg.rs new file mode 100644 index 00000000..46665ee5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h743xg.rs @@ -0,0 +1,924 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h743xi.rs b/embassy-stm32/src/pac/stm32h743xi.rs new file mode 100644 index 00000000..46665ee5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h743xi.rs @@ -0,0 +1,924 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h743zg.rs b/embassy-stm32/src/pac/stm32h743zg.rs new file mode 100644 index 00000000..46665ee5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h743zg.rs @@ -0,0 +1,924 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h743zi.rs b/embassy-stm32/src/pac/stm32h743zi.rs new file mode 100644 index 00000000..46665ee5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h743zi.rs @@ -0,0 +1,924 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h745bg.rs b/embassy-stm32/src/pac/stm32h745bg.rs new file mode 100644 index 00000000..1ae5e2e4 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h745bg.rs @@ -0,0 +1,938 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h745bi.rs b/embassy-stm32/src/pac/stm32h745bi.rs new file mode 100644 index 00000000..1ae5e2e4 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h745bi.rs @@ -0,0 +1,938 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h745ig.rs b/embassy-stm32/src/pac/stm32h745ig.rs new file mode 100644 index 00000000..1ae5e2e4 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h745ig.rs @@ -0,0 +1,938 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h745ii.rs b/embassy-stm32/src/pac/stm32h745ii.rs new file mode 100644 index 00000000..1ae5e2e4 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h745ii.rs @@ -0,0 +1,938 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h745xg.rs b/embassy-stm32/src/pac/stm32h745xg.rs new file mode 100644 index 00000000..1ae5e2e4 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h745xg.rs @@ -0,0 +1,938 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h745xi.rs b/embassy-stm32/src/pac/stm32h745xi.rs new file mode 100644 index 00000000..1ae5e2e4 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h745xi.rs @@ -0,0 +1,938 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h745zg.rs b/embassy-stm32/src/pac/stm32h745zg.rs new file mode 100644 index 00000000..1ae5e2e4 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h745zg.rs @@ -0,0 +1,938 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h745zi.rs b/embassy-stm32/src/pac/stm32h745zi.rs new file mode 100644 index 00000000..1ae5e2e4 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h745zi.rs @@ -0,0 +1,938 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h747ag.rs b/embassy-stm32/src/pac/stm32h747ag.rs new file mode 100644 index 00000000..6af4b325 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h747ag.rs @@ -0,0 +1,941 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h747ai.rs b/embassy-stm32/src/pac/stm32h747ai.rs new file mode 100644 index 00000000..6af4b325 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h747ai.rs @@ -0,0 +1,941 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h747bg.rs b/embassy-stm32/src/pac/stm32h747bg.rs new file mode 100644 index 00000000..6af4b325 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h747bg.rs @@ -0,0 +1,941 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h747bi.rs b/embassy-stm32/src/pac/stm32h747bi.rs new file mode 100644 index 00000000..6af4b325 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h747bi.rs @@ -0,0 +1,941 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h747ig.rs b/embassy-stm32/src/pac/stm32h747ig.rs new file mode 100644 index 00000000..6af4b325 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h747ig.rs @@ -0,0 +1,941 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h747ii.rs b/embassy-stm32/src/pac/stm32h747ii.rs new file mode 100644 index 00000000..6af4b325 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h747ii.rs @@ -0,0 +1,941 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h747xg.rs b/embassy-stm32/src/pac/stm32h747xg.rs new file mode 100644 index 00000000..6af4b325 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h747xg.rs @@ -0,0 +1,941 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h747xi.rs b/embassy-stm32/src/pac/stm32h747xi.rs new file mode 100644 index 00000000..6af4b325 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h747xi.rs @@ -0,0 +1,941 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h747zi.rs b/embassy-stm32/src/pac/stm32h747zi.rs new file mode 100644 index 00000000..6af4b325 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h747zi.rs @@ -0,0 +1,941 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h750ib.rs b/embassy-stm32/src/pac/stm32h750ib.rs new file mode 100644 index 00000000..2144403d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h750ib.rs @@ -0,0 +1,927 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h750vb.rs b/embassy-stm32/src/pac/stm32h750vb.rs new file mode 100644 index 00000000..980984e1 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h750vb.rs @@ -0,0 +1,927 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h750xb.rs b/embassy-stm32/src/pac/stm32h750xb.rs new file mode 100644 index 00000000..2144403d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h750xb.rs @@ -0,0 +1,927 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h750zb.rs b/embassy-stm32/src/pac/stm32h750zb.rs new file mode 100644 index 00000000..2144403d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h750zb.rs @@ -0,0 +1,927 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h753ai.rs b/embassy-stm32/src/pac/stm32h753ai.rs new file mode 100644 index 00000000..2144403d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h753ai.rs @@ -0,0 +1,927 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h753bi.rs b/embassy-stm32/src/pac/stm32h753bi.rs new file mode 100644 index 00000000..2144403d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h753bi.rs @@ -0,0 +1,927 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h753ii.rs b/embassy-stm32/src/pac/stm32h753ii.rs new file mode 100644 index 00000000..2144403d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h753ii.rs @@ -0,0 +1,927 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h753vi.rs b/embassy-stm32/src/pac/stm32h753vi.rs new file mode 100644 index 00000000..2144403d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h753vi.rs @@ -0,0 +1,927 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h753xi.rs b/embassy-stm32/src/pac/stm32h753xi.rs new file mode 100644 index 00000000..2144403d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h753xi.rs @@ -0,0 +1,927 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h753zi.rs b/embassy-stm32/src/pac/stm32h753zi.rs new file mode 100644 index 00000000..2144403d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h753zi.rs @@ -0,0 +1,927 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h755bi.rs b/embassy-stm32/src/pac/stm32h755bi.rs new file mode 100644 index 00000000..434e73a5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h755bi.rs @@ -0,0 +1,941 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h755ii.rs b/embassy-stm32/src/pac/stm32h755ii.rs new file mode 100644 index 00000000..434e73a5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h755ii.rs @@ -0,0 +1,941 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h755xi.rs b/embassy-stm32/src/pac/stm32h755xi.rs new file mode 100644 index 00000000..434e73a5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h755xi.rs @@ -0,0 +1,941 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h755zi.rs b/embassy-stm32/src/pac/stm32h755zi.rs new file mode 100644 index 00000000..434e73a5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h755zi.rs @@ -0,0 +1,941 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h757ai.rs b/embassy-stm32/src/pac/stm32h757ai.rs new file mode 100644 index 00000000..0c225bf3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h757ai.rs @@ -0,0 +1,944 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h757bi.rs b/embassy-stm32/src/pac/stm32h757bi.rs new file mode 100644 index 00000000..0c225bf3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h757bi.rs @@ -0,0 +1,944 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h757ii.rs b/embassy-stm32/src/pac/stm32h757ii.rs new file mode 100644 index 00000000..0c225bf3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h757ii.rs @@ -0,0 +1,944 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h757xi.rs b/embassy-stm32/src/pac/stm32h757xi.rs new file mode 100644 index 00000000..0c225bf3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h757xi.rs @@ -0,0 +1,944 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h757zi.rs b/embassy-stm32/src/pac/stm32h757zi.rs new file mode 100644 index 00000000..0c225bf3 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h757zi.rs @@ -0,0 +1,944 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3ag.rs b/embassy-stm32/src/pac/stm32h7a3ag.rs new file mode 100644 index 00000000..afd38855 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3ag.rs @@ -0,0 +1,908 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3ai.rs b/embassy-stm32/src/pac/stm32h7a3ai.rs new file mode 100644 index 00000000..afd38855 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3ai.rs @@ -0,0 +1,908 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3ig.rs b/embassy-stm32/src/pac/stm32h7a3ig.rs new file mode 100644 index 00000000..afd38855 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3ig.rs @@ -0,0 +1,908 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3ii.rs b/embassy-stm32/src/pac/stm32h7a3ii.rs new file mode 100644 index 00000000..afd38855 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3ii.rs @@ -0,0 +1,908 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3lg.rs b/embassy-stm32/src/pac/stm32h7a3lg.rs new file mode 100644 index 00000000..afd38855 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3lg.rs @@ -0,0 +1,908 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3li.rs b/embassy-stm32/src/pac/stm32h7a3li.rs new file mode 100644 index 00000000..afd38855 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3li.rs @@ -0,0 +1,908 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3ng.rs b/embassy-stm32/src/pac/stm32h7a3ng.rs new file mode 100644 index 00000000..afd38855 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3ng.rs @@ -0,0 +1,908 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3ni.rs b/embassy-stm32/src/pac/stm32h7a3ni.rs new file mode 100644 index 00000000..afd38855 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3ni.rs @@ -0,0 +1,908 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3qi.rs b/embassy-stm32/src/pac/stm32h7a3qi.rs new file mode 100644 index 00000000..afd38855 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3qi.rs @@ -0,0 +1,908 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3rg.rs b/embassy-stm32/src/pac/stm32h7a3rg.rs new file mode 100644 index 00000000..afd38855 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3rg.rs @@ -0,0 +1,908 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3ri.rs b/embassy-stm32/src/pac/stm32h7a3ri.rs new file mode 100644 index 00000000..afd38855 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3ri.rs @@ -0,0 +1,908 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3vg.rs b/embassy-stm32/src/pac/stm32h7a3vg.rs new file mode 100644 index 00000000..afd38855 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3vg.rs @@ -0,0 +1,908 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3vi.rs b/embassy-stm32/src/pac/stm32h7a3vi.rs new file mode 100644 index 00000000..afd38855 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3vi.rs @@ -0,0 +1,908 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3zg.rs b/embassy-stm32/src/pac/stm32h7a3zg.rs new file mode 100644 index 00000000..afd38855 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3zg.rs @@ -0,0 +1,908 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3zi.rs b/embassy-stm32/src/pac/stm32h7a3zi.rs new file mode 100644 index 00000000..afd38855 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3zi.rs @@ -0,0 +1,908 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b0ab.rs b/embassy-stm32/src/pac/stm32h7b0ab.rs new file mode 100644 index 00000000..f5168f8d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b0ab.rs @@ -0,0 +1,917 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b0ib.rs b/embassy-stm32/src/pac/stm32h7b0ib.rs new file mode 100644 index 00000000..f5168f8d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b0ib.rs @@ -0,0 +1,917 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b0rb.rs b/embassy-stm32/src/pac/stm32h7b0rb.rs new file mode 100644 index 00000000..f5168f8d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b0rb.rs @@ -0,0 +1,917 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b0vb.rs b/embassy-stm32/src/pac/stm32h7b0vb.rs new file mode 100644 index 00000000..f5168f8d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b0vb.rs @@ -0,0 +1,917 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b0zb.rs b/embassy-stm32/src/pac/stm32h7b0zb.rs new file mode 100644 index 00000000..f5168f8d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b0zb.rs @@ -0,0 +1,917 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b3ai.rs b/embassy-stm32/src/pac/stm32h7b3ai.rs new file mode 100644 index 00000000..f5168f8d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b3ai.rs @@ -0,0 +1,917 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b3ii.rs b/embassy-stm32/src/pac/stm32h7b3ii.rs new file mode 100644 index 00000000..f5168f8d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b3ii.rs @@ -0,0 +1,917 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b3li.rs b/embassy-stm32/src/pac/stm32h7b3li.rs new file mode 100644 index 00000000..f5168f8d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b3li.rs @@ -0,0 +1,917 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b3ni.rs b/embassy-stm32/src/pac/stm32h7b3ni.rs new file mode 100644 index 00000000..f5168f8d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b3ni.rs @@ -0,0 +1,917 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b3qi.rs b/embassy-stm32/src/pac/stm32h7b3qi.rs new file mode 100644 index 00000000..f5168f8d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b3qi.rs @@ -0,0 +1,917 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b3ri.rs b/embassy-stm32/src/pac/stm32h7b3ri.rs new file mode 100644 index 00000000..f5168f8d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b3ri.rs @@ -0,0 +1,917 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b3vi.rs b/embassy-stm32/src/pac/stm32h7b3vi.rs new file mode 100644 index 00000000..f5168f8d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b3vi.rs @@ -0,0 +1,917 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b3zi.rs b/embassy-stm32/src/pac/stm32h7b3zi.rs new file mode 100644 index 00000000..f5168f8d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b3zi.rs @@ -0,0 +1,917 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1, 0x52007000); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2, 0x48022400); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, + PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, + PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, + PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, + PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, + PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, + PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, + PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, + PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, + PK11, PK12, PK13, PK14, PK15, EXTI, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/sdmmc_v2.rs b/embassy-stm32/src/sdmmc_v2.rs new file mode 100644 index 00000000..b96b9154 --- /dev/null +++ b/embassy-stm32/src/sdmmc_v2.rs @@ -0,0 +1,1078 @@ +use core::marker::PhantomData; +use core::task::{Context, Poll}; + +use embassy::util::{AtomicWaker, OnDrop, Unborrow}; +use embassy_extras::unborrow; +use futures::future::poll_fn; +use sdio_host::{BusWidth, CardCapacity, CardStatus, CurrentState, SDStatus, CID, CSD, OCR, SCR}; + +use crate::fmt::*; +use crate::gpio::AnyPin; +use crate::interrupt; +use crate::pac; +use crate::pac::gpio::Gpio; +use crate::pac::interrupt::{Interrupt, InterruptEnum}; +use crate::pac::sdmmc::Sdmmc as RegBlock; +use crate::time::Hertz; + +/// The signalling scheme used on the SDMMC bus +#[non_exhaustive] +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Signalling { + SDR12, + SDR25, + SDR50, + SDR104, + DDR50, +} + +impl Default for Signalling { + fn default() -> Self { + Signalling::SDR12 + } +} + +/// Errors +#[non_exhaustive] +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Error { + Timeout, + SoftwareTimeout, + UnsupportedCardVersion, + UnsupportedCardType, + Crc, + DataCrcFail, + RxOverFlow, + NoCard, + BadClock, + SignalingSwitchFailed, + PeripheralBusy, +} + +/// A SD command +struct Cmd { + cmd: u8, + arg: u32, + resp: Response, +} + +#[derive(Clone, Copy, Debug, Default)] +/// SD Card +pub struct Card { + /// The type of this card + pub card_type: CardCapacity, + /// Operation Conditions Register + pub ocr: OCR, + /// Relative Card Address + pub rca: u32, + /// Card ID + pub cid: CID, + /// Card Specific Data + pub csd: CSD, + /// SD CARD Configuration Register + pub scr: SCR, + /// SD Status + pub status: SDStatus, +} +impl Card { + /// Size in bytes + pub fn size(&self) -> u64 { + // SDHC / SDXC / SDUC + u64::from(self.csd.block_count()) * 512 + } +} + +/// Indicates transfer direction +enum Dir { + CardToHost, + HostToCard, +} + +#[repr(u8)] +enum PowerCtrl { + Off = 0b00, + On = 0b11, +} + +#[repr(u32)] +#[allow(dead_code)] +#[allow(non_camel_case_types)] +enum CmdAppOper { + VOLTAGE_WINDOW_SD = 0x8010_0000, + HIGH_CAPACITY = 0x4000_0000, + SDMMC_STD_CAPACITY = 0x0000_0000, + SDMMC_CHECK_PATTERN = 0x0000_01AA, + SD_SWITCH_1_8V_CAPACITY = 0x0100_0000, +} + +#[derive(Eq, PartialEq, Copy, Clone)] +enum Response { + None = 0, + Short = 1, + Long = 3, +} + +/// Calculate clock divisor. Returns a SDMMC_CK less than or equal to +/// `sdmmc_ck` in Hertz. +/// +/// Returns `(clk_div, clk_f)`, where `clk_div` is the divisor register +/// value and `clk_f` is the resulting new clock frequency. +fn clk_div(ker_ck: Hertz, sdmmc_ck: u32) -> Result<(u16, Hertz), Error> { + match (ker_ck.0 + sdmmc_ck - 1) / sdmmc_ck { + 0 | 1 => Ok((0, ker_ck)), + x @ 2..=2046 => { + let clk_div = ((x + 1) / 2) as u16; + let clk = Hertz(ker_ck.0 / (clk_div as u32 * 2)); + + Ok((clk_div, clk)) + } + _ => Err(Error::BadClock), + } +} + +struct SdmmcPins { + clk: AnyPin, + cmd: AnyPin, + d0: AnyPin, + d1: Option, + d2: Option, + d3: Option, +} + +impl SdmmcPins { + /// # Safety + /// + /// Must have exclusive access to the gpio(s)' registers + unsafe fn deconfigure(&mut self) { + use crate::gpio::sealed::Pin as _; + use crate::gpio::Pin; + use pac::gpio::vals::Moder; + + let n = self.clk.pin().into(); + self.clk + .block() + .moder() + .modify(|w| w.set_moder(n, Moder::ANALOG)); + + let n = self.cmd.pin().into(); + self.cmd + .block() + .moder() + .modify(|w| w.set_moder(n, Moder::ANALOG)); + + let n = self.d0.pin().into(); + self.d0 + .block() + .moder() + .modify(|w| w.set_moder(n, Moder::ANALOG)); + + if let Some(pin) = &self.d1 { + let n = pin.pin().into(); + pin.block() + .moder() + .modify(|w| w.set_moder(n, Moder::ANALOG)); + } + + if let Some(pin) = &self.d2 { + let n = pin.pin().into(); + pin.block() + .moder() + .modify(|w| w.set_moder(n, Moder::ANALOG)); + } + + if let Some(pin) = &self.d3 { + let n = pin.pin().into(); + pin.block() + .moder() + .modify(|w| w.set_moder(n, Moder::ANALOG)); + } + } +} + +#[repr(transparent)] +pub struct DataBlock { + pub buf: [u32; 128], +} + +/// Sdmmc device +pub struct Sdmmc<'d> { + sdmmc: PhantomData<&'d mut ()>, + regs_addr: u32, + /// SDMMC kernel clock + ker_ck: Hertz, + /// AHB clock + hclk: Hertz, + /// Data bus width + bus_width: BusWidth, + /// Current clock to card + clock: Hertz, + /// Current signalling scheme to card + signalling: Signalling, + /// Card + card: Option, + pins: SdmmcPins, + interrupt_sdmmc1: bool, +} + +impl<'d> Sdmmc<'d> { + #[inline(always)] + fn regs(&mut self) -> RegBlock { + RegBlock(self.regs_addr as _) + } + + /// # Safety + /// + /// Access to `block` registers should be exclusive + unsafe fn configure_pin(block: Gpio, n: usize, afr_num: u8, pup: bool) { + use pac::gpio::vals::{Afr, Moder, Ospeedr, Pupdr}; + + let (afr, n_af) = if n < 8 { (0, n) } else { (1, n - 8) }; + block.afr(afr).modify(|w| w.set_afr(n_af, Afr(afr_num))); + block.moder().modify(|w| w.set_moder(n, Moder::ALTERNATE)); + if pup { + block.pupdr().modify(|w| w.set_pupdr(n, Pupdr::PULLUP)); + } + block + .ospeedr() + .modify(|w| w.set_ospeedr(n, Ospeedr::VERYHIGHSPEED)); + } + + /// # Safety + /// + /// Access to `regs` registers should be exclusive + unsafe fn new_inner(regs: RegBlock, kernel_clk: Hertz) -> Hertz { + // While the SD/SDIO card or eMMC is in identification mode, + // the SDMMC_CK frequency must be less than 400 kHz. + let (clkdiv, clock) = unwrap!(clk_div(kernel_clk, 400_000)); + + regs.clkcr().write(|w| { + w.set_widbus(0); + w.set_clkdiv(clkdiv); + w.set_pwrsav(false); + w.set_negedge(false); + w.set_hwfc_en(true); + }); + + // Power off, writen 00: Clock to the card is stopped; + // D[7:0], CMD, and CK are driven high. + regs.power().modify(|w| w.set_pwrctrl(PowerCtrl::Off as u8)); + + clock + } + + /// # Safety + /// + /// Futures that borrow this type can't be leaked + #[allow(clippy::too_many_arguments)] + pub unsafe fn new_four_width( + _peripheral: impl Unborrow + 'd, + interrupt: u16, + clk_pin: impl Unborrow + 'd, + cmd_pin: impl Unborrow + 'd, + d0_pin: impl Unborrow + 'd, + d1_pin: impl Unborrow + 'd, + d2_pin: impl Unborrow + 'd, + d3_pin: impl Unborrow + 'd, + hclk: Hertz, + kernel_clk: Hertz, + ) -> Self + where + T: Instance, + CLK: CkPin, + CMD: CmdPin, + D0: D0Pin, + D1: D1Pin, + D2: D2Pin, + D3: D3Pin, + { + unborrow!(clk_pin, cmd_pin, d0_pin, d1_pin, d2_pin, d3_pin); + + // Configure Pins + cortex_m::interrupt::free(|_| { + // clk + let block = clk_pin.block(); + let n = clk_pin.pin() as usize; + let afr_num = CLK::AF_NUM; + Self::configure_pin(block, n, afr_num, false); + + // cmd + let block = cmd_pin.block(); + let n = cmd_pin.pin() as usize; + let afr_num = CMD::AF_NUM; + Self::configure_pin(block, n, afr_num, true); + + // d0 + let block = d0_pin.block(); + let n = d0_pin.pin() as usize; + let afr_num = D0::AF_NUM; + Self::configure_pin(block, n, afr_num, true); + + // d1 + let block = d1_pin.block(); + let n = d1_pin.pin() as usize; + let afr_num = D1::AF_NUM; + Self::configure_pin(block, n, afr_num, true); + + // d2 + let block = d2_pin.block(); + let n = d2_pin.pin() as usize; + let afr_num = D2::AF_NUM; + Self::configure_pin(block, n, afr_num, true); + + // d3 + let block = d3_pin.block(); + let n = d3_pin.pin() as usize; + let afr_num = D3::AF_NUM; + Self::configure_pin(block, n, afr_num, true); + }); + + let regs = RegBlock(T::ADDR as _); + let clock = Self::new_inner(regs, kernel_clk); + + let pins = SdmmcPins { + cmd: cmd_pin.degrade(), + clk: clk_pin.degrade(), + d0: d0_pin.degrade(), + d1: Some(d1_pin.degrade()), + d2: Some(d2_pin.degrade()), + d3: Some(d3_pin.degrade()), + }; + + Self { + sdmmc: PhantomData, + regs_addr: T::ADDR, + bus_width: BusWidth::Four, + ker_ck: kernel_clk, + hclk, + clock, + signalling: Default::default(), + card: None, + pins, + interrupt_sdmmc1: interrupt == SDMMC1_INR, + } + } + + /// Initializes card (if present) and sets the bus at the + /// specified frequency. + pub async fn init_card(&mut self, freq: impl Into) -> Result<(), Error> { + let freq = freq.into(); + let regs = self.regs(); + + // NOTE(unsafe) We have exclusive access to the peripheral + unsafe { + regs.power().modify(|w| w.set_pwrctrl(PowerCtrl::On as u8)); + defmt::info!("pwr"); + self.cmd(Cmd::idle(), false)?; + + // Check if cards supports CMD8 (with pattern) + self.cmd(Cmd::hs_send_ext_csd(0x1AA), false)?; + let r1 = regs.respr(0).read().cardstatus1(); + + let mut card = if r1 == 0x1AA { + // Card echoed back the pattern. Must be at least v2 + Card::default() + } else { + return Err(Error::UnsupportedCardVersion); + }; + + defmt::info!("CMD8"); + + let ocr = loop { + // Signal that next command is a app command + self.cmd(Cmd::app_cmd(0), false)?; // CMD55 + + let arg = CmdAppOper::VOLTAGE_WINDOW_SD as u32 + | CmdAppOper::HIGH_CAPACITY as u32 + | CmdAppOper::SD_SWITCH_1_8V_CAPACITY as u32; + + // Initialize card + match self.cmd(Cmd::app_op_cmd(arg), false) { + // ACMD41 + Ok(_) => (), + Err(Error::Crc) => (), + Err(err) => return Err(err), + } + let ocr: OCR = regs.respr(0).read().cardstatus1().into(); + if !ocr.is_busy() { + // Power up done + break ocr; + } + }; + + if ocr.high_capacity() { + // Card is SDHC or SDXC or SDUC + card.card_type = CardCapacity::SDHC; + } else { + card.card_type = CardCapacity::SDSC; + } + card.ocr = ocr; + defmt::info!("OCR"); + + self.cmd(Cmd::all_send_cid(), false)?; // CMD2 + let cid0 = regs.respr(0).read().cardstatus1() as u128; + let cid1 = regs.respr(1).read().cardstatus1() as u128; + let cid2 = regs.respr(2).read().cardstatus1() as u128; + let cid3 = regs.respr(3).read().cardstatus1() as u128; + let cid = (cid0 << 96) | (cid1 << 64) | (cid2 << 32) | (cid3); + card.cid = cid.into(); + + self.cmd(Cmd::send_rel_addr(), false)?; + card.rca = regs.respr(0).read().cardstatus1() >> 16; + + self.cmd(Cmd::send_csd(card.rca << 16), false)?; + let csd0 = regs.respr(0).read().cardstatus1() as u128; + let csd1 = regs.respr(1).read().cardstatus1() as u128; + let csd2 = regs.respr(2).read().cardstatus1() as u128; + let csd3 = regs.respr(3).read().cardstatus1() as u128; + let csd = (csd0 << 96) | (csd1 << 64) | (csd2 << 32) | (csd3); + card.csd = csd.into(); + + self.select_card(Some(&card))?; + + defmt::info!("select"); + self.get_scr(&mut card).await?; + + defmt::info!("scr"); + + // Set bus width + let (width, acmd_arg) = match self.bus_width { + BusWidth::Eight => unimplemented!(), + BusWidth::Four if card.scr.bus_width_four() => (BusWidth::Four, 2), + _ => (BusWidth::One, 0), + }; + self.cmd(Cmd::app_cmd(card.rca << 16), false)?; + self.cmd(Cmd::cmd6(acmd_arg), false)?; + + // CPSMACT and DPSMACT must be 0 to set WIDBUS + self.wait_idle(); + + regs.clkcr().modify(|w| { + w.set_widbus(match width { + BusWidth::One => 0, + BusWidth::Four => 1, + BusWidth::Eight => 2, + _ => self::panic!("Invalid Bus Width"), + }) + }); + + // Set Clock + if freq.0 <= 25_000_000 { + // Final clock frequency + self.clkcr_set_clkdiv(freq.0, width)?; + } else { + // Switch to max clock for SDR12 + self.clkcr_set_clkdiv(25_000_000, width)?; + } + + // Read status + self.card.replace(card); + self.read_sd_status().await?; + + if freq.0 > 25_000_000 { + // Switch to SDR25 + self.signalling = self.switch_signalling_mode(Signalling::SDR25)?; + + if self.signalling == Signalling::SDR25 { + // Set final clock frequency + self.clkcr_set_clkdiv(freq.0, width)?; + + if self.read_status()?.state() != CurrentState::Transfer { + return Err(Error::SignalingSwitchFailed); + } + } + } + // Read status after signalling change + self.read_sd_status().await?; + } + Ok(()) + } + + /// Get a reference to the initialized card + /// + /// # Errors + /// + /// Returns Error::NoCard if [`init_card`](#method.init_card) + /// has not previously succeeded + pub fn card(&self) -> Result<&Card, Error> { + self.card.as_ref().ok_or(Error::NoCard) + } + + /// Get a mutable reference to the initialized card + /// + /// # Errors + /// + /// Returns Error::NoCard if [`init_card`](#method.init_card) + /// has not previously succeeded + pub fn card_mut(&mut self) -> Result<&mut Card, Error> { + self.card.as_mut().ok_or(Error::NoCard) + } + + pub async fn read_block( + &mut self, + block_idx: u32, + buffer: &mut DataBlock, + ) -> Result<(), Error> { + self::todo!() + } + + /// Get the current SDMMC bus clock + pub fn clock(&self) -> Hertz { + self.clock + } + + /// Wait idle on DOSNACT and CPSMACT + #[inline(always)] + fn wait_idle(&mut self) { + let regs = self.regs(); + + // NOTE(unsafe) Atomic read with no side-effects + unsafe { + while { + let status = regs.star().read(); + status.dpsmact() || status.cpsmact() + } {} + } + } + + /// # Safety + /// + /// `buffer_addr` must be valid for the whole transfer and word aligned + unsafe fn prepare_datapath_transfer( + &mut self, + buffer_addr: u32, + length_bytes: u32, + block_size: u8, + direction: Dir, + ) { + self::assert!(block_size <= 14, "Block size up to 2^14 bytes"); + let regs = self.regs(); + + let dtdir = match direction { + Dir::CardToHost => true, + Dir::HostToCard => false, + }; + + // Command AND Data state machines must be idle + self.wait_idle(); + Self::clear_interrupt_flags(regs); + + // NOTE(unsafe) We have exclusive access to the regisers + + // TODO: Make this configurable + regs.dtimer().write(|w| w.set_datatime(5_000_000)); + regs.dlenr().write(|w| w.set_datalength(length_bytes)); + + regs.idmabase0r().write(|w| w.set_idmabase0(buffer_addr)); + regs.idmactrlr().modify(|w| w.set_idmaen(true)); + regs.dctrl().modify(|w| { + w.set_dblocksize(block_size); + w.set_dtdir(dtdir); + }); + } + + /// Sets the CLKDIV field in CLKCR. Updates clock field in self + fn clkcr_set_clkdiv(&mut self, freq: u32, width: BusWidth) -> Result<(), Error> { + let regs = self.regs(); + + let (clkdiv, new_clock) = clk_div(self.ker_ck, freq)?; + // Enforce AHB and SDMMC_CK clock relation. See RM0433 Rev 7 + // Section 55.5.8 + let sdmmc_bus_bandwidth = new_clock.0 * (width as u32); + self::assert!(self.hclk.0 > 3 * sdmmc_bus_bandwidth / 32); + self.clock = new_clock; + + // NOTE(unsafe) We have exclusive access to the regblock + unsafe { + // CPSMACT and DPSMACT must be 0 to set CLKDIV + self.wait_idle(); + regs.clkcr().modify(|w| w.set_clkdiv(clkdiv)); + } + + Ok(()) + } + + /// Switch mode using CMD6. + /// + /// Attempt to set a new signalling mode. The selected + /// signalling mode is returned. Expects the current clock + /// frequency to be > 12.5MHz. + fn switch_signalling_mode(&self, signalling: Signalling) -> Result { + self::todo!() + } + + /// Query the card status (CMD13, returns R1) + /// + fn read_status(&mut self) -> Result { + let regs = self.regs(); + let rca = self.card()?.rca; + + self.cmd(Cmd::card_status(rca << 16), false)?; // CMD13 + + // NOTE(unsafe) Atomic read with no side-effects + let r1 = unsafe { regs.respr(0).read().cardstatus1() }; + Ok(r1.into()) + } + + /// Reads the SD Status (ACMD13) + async fn read_sd_status(&mut self) -> Result<(), Error> { + let card = self.card()?; + let rca = card.rca; + self.cmd(Cmd::set_block_length(64), false)?; // CMD16 + self.cmd(Cmd::app_cmd(rca << 16), false)?; // APP + + let mut status = [0u32; 16]; + let status_addr = &mut status as *mut [u32; 16] as u32; + + // Arm `OnDrop` after the buffer, so it will be dropped first + let regs = self.regs(); + let on_drop = OnDrop::new(move || unsafe { Self::on_drop(regs) }); + + unsafe { + self.prepare_datapath_transfer(status_addr, 64, 6, Dir::CardToHost); + Self::data_interrupts(regs, true); + } + self.cmd(Cmd::card_status(0), true)?; + + let res = poll_fn(|cx| { + self.store_waker_and_unmask(&cx); + let status = unsafe { regs.star().read() }; + + if status.dcrcfail() { + return Poll::Ready(Err(Error::Crc)); + } else if status.dtimeout() { + return Poll::Ready(Err(Error::Timeout)); + } else if status.dataend() { + return Poll::Ready(Ok(())); + } + Poll::Pending + }) + .await; + + unsafe { + Self::data_interrupts(regs, false); + } + Self::clear_interrupt_flags(regs); + + if let Ok(_) = &res { + on_drop.defuse(); + unsafe { + regs.idmactrlr().modify(|w| w.set_idmaen(false)); + } + for byte in status.iter_mut() { + *byte = u32::from_be(*byte); + } + self.card_mut()?.status = status.into(); + } + res + } + + /// Select one card and place it into the _Tranfer State_ + /// + /// If `None` is specifed for `card`, all cards are put back into + /// _Stand-by State_ + fn select_card(&mut self, card: Option<&Card>) -> Result<(), Error> { + // Determine Relative Card Address (RCA) of given card + let rca = card.map(|c| c.rca << 16).unwrap_or(0); + + let r = self.cmd(Cmd::sel_desel_card(rca), false); + match (r, rca) { + (Err(Error::Timeout), 0) => Ok(()), + _ => r, + } + } + + /// Clear flags in interrupt clear register + #[inline(always)] + fn clear_interrupt_flags(regs: RegBlock) { + // NOTE(unsafe) Atomic write + unsafe { + regs.icr().write(|w| { + w.set_ccrcfailc(true); + w.set_dcrcfailc(true); + w.set_ctimeoutc(true); + w.set_dtimeoutc(true); + w.set_txunderrc(true); + w.set_rxoverrc(true); + w.set_cmdsentc(true); + w.set_dataendc(true); + w.set_dholdc(true); + w.set_dbckendc(true); + w.set_dabortc(true); + w.set_busyd0endc(true); + w.set_sdioitc(true); + w.set_ackfailc(true); + w.set_acktimeoutc(true); + w.set_vswendc(true); + w.set_ckstopc(true); + w.set_idmatec(true); + w.set_idmabtcc(true); + }); + } + } + + /// Enables the interrupts for data transfer + /// + /// # Safety + /// + /// Access to `regs` must be exclusive + #[inline(always)] + unsafe fn data_interrupts(regs: RegBlock, enable: bool) { + regs.maskr().modify(|w| { + w.set_dcrcfailie(enable); + w.set_dtimeoutie(enable); + w.set_dataendie(enable); + w.set_dabortie(enable); + }); + } + + async fn get_scr(&mut self, card: &mut Card) -> Result<(), Error> { + // Read the the 64-bit SCR register + self.cmd(Cmd::set_block_length(8), false)?; // CMD16 + self.cmd(Cmd::app_cmd(card.rca << 16), false)?; + + let mut scr = [0u32; 2]; + let scr_addr = &mut scr as *mut u32 as u32; + + // Arm `OnDrop` after the buffer, so it will be dropped first + let regs = self.regs(); + let on_drop = OnDrop::new(move || unsafe { Self::on_drop(regs) }); + + unsafe { + self.prepare_datapath_transfer(scr_addr, 8, 3, Dir::CardToHost); + Self::data_interrupts(regs, true); + } + self.cmd(Cmd::cmd51(), true)?; + + let res = poll_fn(|cx| { + self.store_waker_and_unmask(&cx); + let status = unsafe { regs.star().read() }; + + if status.dcrcfail() { + return Poll::Ready(Err(Error::Crc)); + } else if status.dtimeout() { + return Poll::Ready(Err(Error::Timeout)); + } else if status.dataend() { + return Poll::Ready(Ok(())); + } + Poll::Pending + }) + .await; + + unsafe { + Self::data_interrupts(regs, false); + } + Self::clear_interrupt_flags(regs); + + if let Ok(_) = &res { + on_drop.defuse(); + + unsafe { + regs.idmactrlr().modify(|w| w.set_idmaen(false)); + let scr_bytes = &*(&scr as *const [u32; 2] as *const [u8; 8]); + card.scr = SCR(u64::from_be_bytes(*scr_bytes)); + } + } + res + } + + /// Send command to card + fn cmd(&mut self, cmd: Cmd, data: bool) -> Result<(), Error> { + let regs = self.regs(); + + Self::clear_interrupt_flags(regs); + // NOTE(safety) Atomic operations + unsafe { + // CP state machine must be idle + while regs.star().read().cpsmact() {} + defmt::info!("cpsma idle"); + + // Command arg + regs.argr().write(|w| w.set_cmdarg(cmd.arg)); + + // Special mode in CP State Machine + // CMD12: Stop Transmission + let cpsm_stop_transmission = cmd.cmd == 12; + + // Command index and start CP State Machine + regs.cmdr().write(|w| { + w.set_waitint(false); + w.set_waitresp(cmd.resp as u8); + w.set_cmdstop(cpsm_stop_transmission); + w.set_cmdindex(cmd.cmd); + w.set_cpsmen(true); + w.set_cmdtrans(data); + }); + + // TODO: Check if this timeout is necessary + let mut timeout: u32 = 0xFFFF_FFFF; + + let mut status; + if cmd.resp == Response::None { + // Wait for CMDSENT or a timeout + while { + status = regs.star().read(); + !(status.ctimeout() || status.cmdsent()) && timeout > 0 + } { + timeout -= 1; + } + } else { + // Wait for CMDREND or CCRCFAIL or a timeout + while { + status = regs.star().read(); + !(status.ctimeout() || status.cmdrend() || status.ccrcfail()) && timeout > 0 + } { + timeout -= 1; + } + } + + if status.ctimeout() { + return Err(Error::Timeout); + } else if timeout == 0 { + return Err(Error::SoftwareTimeout); + } else if status.ccrcfail() { + return Err(Error::Crc); + } + + Ok(()) + } + } + + fn store_waker_and_unmask(&self, cx: &Context) { + use cortex_m::peripheral::NVIC; + + // NOTE(unsafe) We own the interrupt and can unmask it, it won't cause unsoundness + unsafe { + if self.interrupt_sdmmc1 { + WAKER_1.register(cx.waker()); + NVIC::unmask(InterruptEnum::SDMMC1); + } else { + WAKER_2.register(cx.waker()); + NVIC::unmask(InterruptEnum::SDMMC2); + } + } + } + + /// # Safety + /// + /// Ensure that `regs` has exclusive access to the regblocks + unsafe fn on_drop(regs: RegBlock) { + if regs.star().read().dpsmact() { + // Send abort + // CP state machine must be idle + while regs.star().read().cpsmact() {} + + // Command arg + regs.argr().write(|w| w.set_cmdarg(0)); + + // Command index and start CP State Machine + regs.cmdr().write(|w| { + w.set_waitint(false); + w.set_waitresp(Response::Short as u8); + w.set_cmdstop(true); + w.set_cmdindex(12); + w.set_cpsmen(true); + w.set_cmdtrans(false); + }); + + // Wait for the abort + while regs.star().read().dpsmact() {} + } + Self::data_interrupts(regs, false); + Self::clear_interrupt_flags(regs); + regs.idmactrlr().modify(|w| w.set_idmaen(false)); + } +} + +impl<'d> Drop for Sdmmc<'d> { + fn drop(&mut self) { + unsafe { + Self::on_drop(self.regs()); + } + + // NOTE(unsafe) With `free` we will have exclusive access to the registers + cortex_m::interrupt::free(|_| unsafe { + self.pins.deconfigure(); + }) + } +} + +/// SD card Commands +impl Cmd { + const fn new(cmd: u8, arg: u32, resp: Response) -> Cmd { + Cmd { cmd, arg, resp } + } + + /// CMD0: Idle + const fn idle() -> Cmd { + Cmd::new(0, 0, Response::None) + } + + /// CMD2: Send CID + const fn all_send_cid() -> Cmd { + Cmd::new(2, 0, Response::Long) + } + + /// CMD3: Send Relative Address + const fn send_rel_addr() -> Cmd { + Cmd::new(3, 0, Response::Short) + } + + /// CMD6: Switch Function Command + /// ACMD6: Bus Width + const fn cmd6(arg: u32) -> Cmd { + Cmd::new(6, arg, Response::Short) + } + + /// CMD7: Select one card and put it into the _Tranfer State_ + const fn sel_desel_card(rca: u32) -> Cmd { + Cmd::new(7, rca, Response::Short) + } + + /// CMD8: + const fn hs_send_ext_csd(arg: u32) -> Cmd { + Cmd::new(8, arg, Response::Short) + } + + /// CMD9: + const fn send_csd(rca: u32) -> Cmd { + Cmd::new(9, rca, Response::Long) + } + + /// CMD12: + const fn stop_transmission() -> Cmd { + Cmd::new(12, 0, Response::Short) + } + + /// CMD13: Ask card to send status register + /// ACMD13: SD Status + const fn card_status(rca: u32) -> Cmd { + Cmd::new(13, rca, Response::Short) + } + + /// CMD16: + const fn set_block_length(blocklen: u32) -> Cmd { + Cmd::new(16, blocklen, Response::Short) + } + + /// CMD17: Block Read + const fn read_single_block(addr: u32) -> Cmd { + Cmd::new(17, addr, Response::Short) + } + + /// CMD18: Multiple Block Read + const fn read_multiple_blocks(addr: u32) -> Cmd { + Cmd::new(18, addr, Response::Short) + } + + /// CMD24: Block Write + const fn write_single_block(addr: u32) -> Cmd { + Cmd::new(24, addr, Response::Short) + } + + const fn app_op_cmd(arg: u32) -> Cmd { + Cmd::new(41, arg, Response::Short) + } + + const fn cmd51() -> Cmd { + Cmd::new(51, 0, Response::Short) + } + + /// App Command. Indicates that next command will be a app command + const fn app_cmd(rca: u32) -> Cmd { + Cmd::new(55, rca, Response::Short) + } +} + +////////////////////////////////////////////////////// + +const SDMMC1_INR: u16 = 49; +static WAKER_1: AtomicWaker = AtomicWaker::new(); +static WAKER_2: AtomicWaker = AtomicWaker::new(); + +#[interrupt] +unsafe fn SDMMC1() { + cortex_m::peripheral::NVIC::mask(InterruptEnum::SDMMC1); + WAKER_1.wake(); +} + +#[cfg(feature = "2sdmmc")] +#[interrupt] +unsafe fn SDMMC2() { + cortex_m::peripheral::NVIC::mask(InterruptEnum::SDMMC2); + WAKER_2.wake(); +} + +pub(crate) mod sealed { + use super::*; + use crate::gpio::Pin as GpioPin; + + pub trait Instance { + const ADDR: u32; + type Interrupt: Interrupt; + } + pub trait CkPin: GpioPin { + const AF_NUM: u8; + } + pub trait CmdPin: GpioPin { + const AF_NUM: u8; + } + pub trait D0Pin: GpioPin { + const AF_NUM: u8; + } + pub trait D1Pin: GpioPin { + const AF_NUM: u8; + } + pub trait D2Pin: GpioPin { + const AF_NUM: u8; + } + pub trait D3Pin: GpioPin { + const AF_NUM: u8; + } + pub trait D4Pin: GpioPin { + const AF_NUM: u8; + } + pub trait D5Pin: GpioPin { + const AF_NUM: u8; + } + pub trait D6Pin: GpioPin { + const AF_NUM: u8; + } + pub trait D7Pin: GpioPin { + const AF_NUM: u8; + } +} + +pub trait Instance: sealed::Instance {} +pub trait CkPin: sealed::CkPin {} +pub trait CmdPin: sealed::CmdPin {} +pub trait D0Pin: sealed::D0Pin {} +pub trait D1Pin: sealed::D1Pin {} +pub trait D2Pin: sealed::D2Pin {} +pub trait D3Pin: sealed::D3Pin {} +pub trait D4Pin: sealed::D4Pin {} +pub trait D5Pin: sealed::D5Pin {} +pub trait D6Pin: sealed::D6Pin {} +pub trait D7Pin: sealed::D7Pin {} + +macro_rules! impl_sdmmc { + ($inst:ident, $addr:expr) => { + impl crate::sdmmc_v2::sealed::Instance for peripherals::$inst { + const ADDR: u32 = $addr; + type Interrupt = interrupt::$inst; + } + + impl crate::sdmmc_v2::Instance for peripherals::$inst {} + }; +} + +macro_rules! impl_sdmmc_pin { + ($inst:ident, $func:ident, $pin:ident, $num:expr) => { + impl crate::sdmmc_v2::sealed::$func for peripherals::$pin { + const AF_NUM: u8 = $num; + } + + impl crate::sdmmc_v2::$func for peripherals::$pin {} + }; +}