stm32/rcc: use more PLL etc enums from PAC.
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@@ -26,13 +26,13 @@ pub const HSI48_FREQ: Hertz = Hertz(48_000_000);
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/// LSI speed
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pub const LSI_FREQ: Hertz = Hertz(32_000);
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const VCO_RANGE: RangeInclusive<u32> = 150_000_000..=420_000_000;
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const VCO_RANGE: RangeInclusive<Hertz> = Hertz(150_000_000)..=Hertz(420_000_000);
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#[cfg(any(stm32h5, pwr_h7rm0455))]
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const VCO_WIDE_RANGE: RangeInclusive<u32> = 128_000_000..=560_000_000;
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const VCO_WIDE_RANGE: RangeInclusive<Hertz> = Hertz(128_000_000)..=Hertz(560_000_000);
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#[cfg(pwr_h7rm0468)]
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const VCO_WIDE_RANGE: RangeInclusive<u32> = 192_000_000..=836_000_000;
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const VCO_WIDE_RANGE: RangeInclusive<Hertz> = Hertz(192_000_000)..=Hertz(836_000_000);
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#[cfg(any(pwr_h7rm0399, pwr_h7rm0433))]
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const VCO_WIDE_RANGE: RangeInclusive<u32> = 192_000_000..=960_000_000;
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const VCO_WIDE_RANGE: RangeInclusive<Hertz> = Hertz(192_000_000)..=Hertz(960_000_000);
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pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Ppre as APBPrescaler};
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@@ -641,9 +641,9 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
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let wide_allowed = ref_range != Pllrge::RANGE1;
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let vco_clk = ref_clk * config.mul;
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let vco_range = if VCO_RANGE.contains(&vco_clk.0) {
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let vco_range = if VCO_RANGE.contains(&vco_clk) {
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Pllvcosel::MEDIUMVCO
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} else if wide_allowed && VCO_WIDE_RANGE.contains(&vco_clk.0) {
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} else if wide_allowed && VCO_WIDE_RANGE.contains(&vco_clk) {
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Pllvcosel::WIDEVCO
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} else {
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panic!("pll vco_clk out of range: {} mhz", vco_clk.0)
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