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Move HSE config out of main clock mux

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This makes the configuration more flexible and closer to the underlying
configuration register structure. For example, we could use HSI for the
system clock, but use HSE to output a clock with MCO.
This commit is contained in:
Joonas Javanainen 2022-04-09 17:40:04 +03:00
parent 2f43969dd4
commit 0cfe1dc9df
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GPG Key ID: D39CCA5CB19B9179
1 changed files with 24 additions and 8 deletions
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32
embassy-stm32/src/rcc/f2.rs
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@ -9,10 +9,16 @@ use crate::time::Hertz;
/// HSI speed /// HSI speed
pub const HSI: Hertz = Hertz(16_000_000); pub const HSI: Hertz = Hertz(16_000_000);
#[derive(Clone, Copy)]
pub struct HSEConfig {
pub frequency: Hertz,
pub source: HSESrc,
}
/// System clock mux source /// System clock mux source
#[derive(Clone, Copy)] #[derive(Clone, Copy)]
pub enum ClockSrc { pub enum ClockSrc {
HSE(Hertz, HSESrc), HSE,
HSI, HSI,
} }
@ -206,6 +212,7 @@ impl VoltageRange {
/// Clocks configuration /// Clocks configuration
pub struct Config { pub struct Config {
pub hse: Option<HSEConfig>,
pub mux: ClockSrc, pub mux: ClockSrc,
pub voltage: VoltageRange, pub voltage: VoltageRange,
pub ahb_pre: AHBPrescaler, pub ahb_pre: AHBPrescaler,
@ -217,6 +224,7 @@ impl Default for Config {
#[inline] #[inline]
fn default() -> Config { fn default() -> Config {
Config { Config {
hse: None,
voltage: VoltageRange::Min1V8, voltage: VoltageRange::Min1V8,
mux: ClockSrc::HSI, mux: ClockSrc::HSI,
ahb_pre: AHBPrescaler::NotDivided, ahb_pre: AHBPrescaler::NotDivided,
@ -238,18 +246,26 @@ unsafe fn enable_hse(source: HSESrc) {
while !RCC.cr().read().hserdy() {} while !RCC.cr().read().hserdy() {}
} }
#[inline]
unsafe fn enable_hsi() {
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
}
pub(crate) unsafe fn init(config: Config) { pub(crate) unsafe fn init(config: Config) {
if let Some(hse_config) = config.hse {
enable_hse(hse_config.source);
}
let (sys_clk, sw) = match config.mux { let (sys_clk, sw) = match config.mux {
ClockSrc::HSI => { ClockSrc::HSI => {
// Enable HSI enable_hsi();
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
(HSI, Sw::HSI) (HSI, Sw::HSI)
} }
ClockSrc::HSE(freq, source) => { ClockSrc::HSE => {
enable_hse(source); let hse_config = config
(freq, Sw::HSE) .hse
.expect("HSE must be configured to be used as system clock");
(hse_config.frequency, Sw::HSE)
} }
}; };
// RM0033 Figure 9. Clock tree suggests max SYSCLK/HCLK is 168 MHz, but datasheet specifies PLL // RM0033 Figure 9. Clock tree suggests max SYSCLK/HCLK is 168 MHz, but datasheet specifies PLL