Cargo fmt.

This commit is contained in:
Bob McWhirter 2021-05-17 13:58:49 -04:00
parent 1872824d56
commit 0d1a0934c4
2 changed files with 9 additions and 9 deletions

View File

@ -4,7 +4,7 @@ use crate::gpio::{AnyPin, Pin};
use crate::pac::gpio::vals::{Afr, Moder}; use crate::pac::gpio::vals::{Afr, Moder};
use crate::pac::gpio::Gpio; use crate::pac::gpio::Gpio;
use crate::pac::spi; use crate::pac::spi;
use crate::spi::{ByteOrder, Config, Instance, MisoPin, MosiPin, SckPin, WordSize, Error}; use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize};
use crate::time::Hertz; use crate::time::Hertz;
use core::marker::PhantomData; use core::marker::PhantomData;
use embassy::util::Unborrow; use embassy::util::Unborrow;

View File

@ -4,7 +4,7 @@ use crate::gpio::{AnyPin, Pin};
use crate::pac::gpio::vals::{Afr, Moder}; use crate::pac::gpio::vals::{Afr, Moder};
use crate::pac::gpio::Gpio; use crate::pac::gpio::Gpio;
use crate::pac::spi; use crate::pac::spi;
use crate::spi::{ByteOrder, Config, Instance, MisoPin, MosiPin, SckPin, WordSize, Error}; use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize};
use crate::time::Hertz; use crate::time::Hertz;
use core::marker::PhantomData; use core::marker::PhantomData;
use embassy::util::Unborrow; use embassy::util::Unborrow;
@ -38,10 +38,10 @@ pub struct Spi<'d, T: Instance> {
impl<'d, T: Instance> Spi<'d, T> { impl<'d, T: Instance> Spi<'d, T> {
pub fn new<F>( pub fn new<F>(
pclk: Hertz, pclk: Hertz,
peri: impl Unborrow<Target=T> + 'd, peri: impl Unborrow<Target = T> + 'd,
sck: impl Unborrow<Target=impl SckPin<T>>, sck: impl Unborrow<Target = impl SckPin<T>>,
mosi: impl Unborrow<Target=impl MosiPin<T>>, mosi: impl Unborrow<Target = impl MosiPin<T>>,
miso: impl Unborrow<Target=impl MisoPin<T>>, miso: impl Unborrow<Target = impl MisoPin<T>>,
freq: F, freq: F,
config: Config, config: Config,
) -> Self ) -> Self
@ -210,7 +210,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> {
unsafe { unsafe {
regs.txdr().write(|reg| reg.0 = *word as u32); regs.txdr().write(|reg| reg.0 = *word as u32);
} }
while unsafe { ! regs.sr().read().rxp() } { while unsafe { !regs.sr().read().rxp() } {
// spin waiting for inbound to shift in. // spin waiting for inbound to shift in.
} }
*word = unsafe { regs.rxdr().read().0 as u8 }; *word = unsafe { regs.rxdr().read().0 as u8 };