Cargo fmt.
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1872824d56
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@ -4,7 +4,7 @@ use crate::gpio::{AnyPin, Pin};
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use crate::pac::gpio::vals::{Afr, Moder};
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use crate::pac::gpio::vals::{Afr, Moder};
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use crate::pac::gpio::Gpio;
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use crate::pac::gpio::Gpio;
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use crate::pac::spi;
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use crate::pac::spi;
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use crate::spi::{ByteOrder, Config, Instance, MisoPin, MosiPin, SckPin, WordSize, Error};
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use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize};
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use crate::time::Hertz;
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use crate::time::Hertz;
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use core::marker::PhantomData;
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use core::marker::PhantomData;
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use embassy::util::Unborrow;
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use embassy::util::Unborrow;
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@ -4,7 +4,7 @@ use crate::gpio::{AnyPin, Pin};
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use crate::pac::gpio::vals::{Afr, Moder};
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use crate::pac::gpio::vals::{Afr, Moder};
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use crate::pac::gpio::Gpio;
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use crate::pac::gpio::Gpio;
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use crate::pac::spi;
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use crate::pac::spi;
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use crate::spi::{ByteOrder, Config, Instance, MisoPin, MosiPin, SckPin, WordSize, Error};
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use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize};
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use crate::time::Hertz;
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use crate::time::Hertz;
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use core::marker::PhantomData;
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use core::marker::PhantomData;
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use embassy::util::Unborrow;
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use embassy::util::Unborrow;
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@ -38,15 +38,15 @@ pub struct Spi<'d, T: Instance> {
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impl<'d, T: Instance> Spi<'d, T> {
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impl<'d, T: Instance> Spi<'d, T> {
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pub fn new<F>(
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pub fn new<F>(
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pclk: Hertz,
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pclk: Hertz,
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peri: impl Unborrow<Target=T> + 'd,
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peri: impl Unborrow<Target = T> + 'd,
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sck: impl Unborrow<Target=impl SckPin<T>>,
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sck: impl Unborrow<Target = impl SckPin<T>>,
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mosi: impl Unborrow<Target=impl MosiPin<T>>,
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mosi: impl Unborrow<Target = impl MosiPin<T>>,
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miso: impl Unborrow<Target=impl MisoPin<T>>,
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miso: impl Unborrow<Target = impl MisoPin<T>>,
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freq: F,
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freq: F,
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config: Config,
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config: Config,
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) -> Self
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) -> Self
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where
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where
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F: Into<Hertz>,
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F: Into<Hertz>,
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{
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{
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unborrow!(peri);
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unborrow!(peri);
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unborrow!(sck, mosi, miso);
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unborrow!(sck, mosi, miso);
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@ -210,7 +210,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> {
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unsafe {
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unsafe {
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regs.txdr().write(|reg| reg.0 = *word as u32);
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regs.txdr().write(|reg| reg.0 = *word as u32);
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}
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}
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while unsafe { ! regs.sr().read().rxp() } {
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while unsafe { !regs.sr().read().rxp() } {
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// spin waiting for inbound to shift in.
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// spin waiting for inbound to shift in.
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}
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}
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*word = unsafe { regs.rxdr().read().0 as u8 };
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*word = unsafe { regs.rxdr().read().0 as u8 };
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