adc: enable ADC and clock selection for STM32WLx
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@ -13,7 +13,7 @@ pub const VREF_CALIB_MV: u32 = 3000;
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/// configuration.
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fn enable() {
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critical_section::with(|_| {
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#[cfg(stm32h7)]
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#[cfg(any(stm32h7, stm32wl))]
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crate::pac::RCC.apb2enr().modify(|w| w.set_adcen(true));
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#[cfg(stm32g0)]
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crate::pac::RCC.apbenr2().modify(|w| w.set_adcen(true));
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