From 0d80a95e5415d9baf5a25fa6f7cb04b4d5d89827 Mon Sep 17 00:00:00 2001 From: Alpha3__0 Date: Thu, 25 May 2023 11:33:29 -0700 Subject: [PATCH] Implement eh 0.2.* serial::Write for Uart/UartTx --- embassy-rp/src/uart/mod.rs | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/embassy-rp/src/uart/mod.rs b/embassy-rp/src/uart/mod.rs index 7234336b..7bd7be41 100644 --- a/embassy-rp/src/uart/mod.rs +++ b/embassy-rp/src/uart/mod.rs @@ -755,6 +755,32 @@ mod eh02 { } } + impl<'d, T: Instance, M: Mode> embedded_hal_02::serial::Write for UartTx<'d, T, M> { + type Error = Error; + + fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> { + let r = T::regs(); + unsafe { + if r.uartfr().read().txff() { + return Err(nb::Error::WouldBlock); + } + + r.uartdr().write(|w| w.set_data(word)); + } + Ok(()) + } + + fn flush(&mut self) -> nb::Result<(), Self::Error> { + let r = T::regs(); + unsafe { + if !r.uartfr().read().txfe() { + return Err(nb::Error::WouldBlock); + } + } + Ok(()) + } + } + impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::serial::Write for UartTx<'d, T, M> { type Error = Error; @@ -775,6 +801,18 @@ mod eh02 { } } + impl<'d, T: Instance, M: Mode> embedded_hal_02::serial::Write for Uart<'d, T, M> { + type Error = Error; + + fn write(&mut self, word: u8) -> Result<(), nb::Error> { + embedded_hal_02::serial::Write::write(&mut self.tx, word) + } + + fn flush(&mut self) -> Result<(), nb::Error> { + embedded_hal_02::serial::Write::flush(&mut self.tx) + } + } + impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::serial::Write for Uart<'d, T, M> { type Error = Error;