Interrupts, async, sine oscillator
This commit is contained in:
Christian Perez Llamas
@ -2,17 +2,18 @@
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//! I2S
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//use core::future::poll_fn;
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//use core::sync::atomic::{compiler_fence, Ordering};
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//use core::task::Poll;
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use core::future::poll_fn;
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use core::sync::atomic::{compiler_fence, Ordering};
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use core::task::Poll;
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//use embassy_hal_common::drop::OnDrop;
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use embassy_cortex_m::interrupt::{InterruptExt, Priority};
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use embassy_hal_common::drop::OnDrop;
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use embassy_hal_common::{into_ref, PeripheralRef};
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//use crate::gpio::sealed::Pin as _;
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use crate::gpio::{AnyPin, Pin as GpioPin};
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use crate::interrupt::Interrupt;
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use crate::pac::i2s::CONFIG;
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use crate::pac::i2s::{RegisterBlock, CONFIG, PSEL};
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use crate::Peripheral;
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// TODO: Define those in lib.rs somewhere else
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@ -35,10 +36,39 @@ pub enum Error {
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// TODO: add other error variants.
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}
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pub const MODE_MASTER_8000: Mode = Mode::Master {
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freq: MckFreq::_32MDiv125,
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ratio: Ratio::_32x,
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}; // error = 0
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pub const MODE_MASTER_11025: Mode = Mode::Master {
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freq: MckFreq::_32MDiv15,
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ratio: Ratio::_192x,
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}; // error = 86
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pub const MODE_MASTER_16000: Mode = Mode::Master {
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freq: MckFreq::_32MDiv21,
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ratio: Ratio::_96x,
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}; // error = 127
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pub const MODE_MASTER_22050: Mode = Mode::Master {
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freq: MckFreq::_32MDiv15,
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ratio: Ratio::_96x,
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}; // error = 172
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pub const MODE_MASTER_32000: Mode = Mode::Master {
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freq: MckFreq::_32MDiv21,
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ratio: Ratio::_48x,
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}; // error = 254
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pub const MODE_MASTER_44100: Mode = Mode::Master {
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freq: MckFreq::_32MDiv15,
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ratio: Ratio::_48x,
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}; // error = 344
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pub const MODE_MASTER_48000: Mode = Mode::Master {
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freq: MckFreq::_32MDiv21,
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ratio: Ratio::_32x,
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}; // error = 381
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#[derive(Clone)]
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#[non_exhaustive]
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pub struct Config {
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pub ratio: Ratio,
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pub mode: Mode,
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pub swidth: SampleWidth,
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pub align: Align,
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pub format: Format,
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@ -48,7 +78,7 @@ pub struct Config {
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impl Default for Config {
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fn default() -> Self {
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Self {
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ratio: Ratio::_32x,
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mode: MODE_MASTER_32000,
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swidth: SampleWidth::_16bit,
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align: Align::Left,
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format: Format::I2S,
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@ -57,6 +87,66 @@ impl Default for Config {
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}
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}
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/// I2S Mode
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum Mode {
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Master { freq: MckFreq, ratio: Ratio },
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Slave,
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}
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impl Mode {
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pub fn sample_rate(&self) -> Option<u32> {
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match self {
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Mode::Master { freq, ratio } => Some(freq.to_frequency() / ratio.to_divisor()),
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Mode::Slave => None,
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}
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}
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}
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/// Master clock generator frequency.
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum MckFreq {
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_32MDiv8,
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_32MDiv10,
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_32MDiv11,
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_32MDiv15,
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_32MDiv16,
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_32MDiv21,
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_32MDiv23,
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_32MDiv30,
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_32MDiv31,
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_32MDiv32,
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_32MDiv42,
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_32MDiv63,
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_32MDiv125,
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}
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impl MckFreq {
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const REGISTER_VALUES: &[u32] = &[
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0x20000000, 0x18000000, 0x16000000, 0x11000000, 0x10000000, 0x0C000000, 0x0B000000, 0x08800000, 0x08400000,
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0x08000000, 0x06000000, 0x04100000, 0x020C0000,
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];
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const FREQUENCIES: &[u32] = &[
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4000000, 3200000, 2909090, 2133333, 2000000, 1523809, 1391304, 1066666, 1032258, 1000000, 761904, 507936,
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256000,
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];
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pub fn to_register_value(&self) -> u32 {
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Self::REGISTER_VALUES[usize::from(*self)]
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}
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pub fn to_frequency(&self) -> u32 {
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Self::FREQUENCIES[usize::from(*self)]
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}
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}
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impl From<MckFreq> for usize {
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fn from(variant: MckFreq) -> Self {
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variant as _
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}
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}
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/// MCK / LRCK ratio.
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum Ratio {
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@ -71,6 +161,14 @@ pub enum Ratio {
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_512x,
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}
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impl Ratio {
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const RATIOS: &[u32] = &[32, 48, 64, 96, 128, 192, 256, 384, 512];
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pub fn to_divisor(&self) -> u32 {
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Self::RATIOS[u8::from(*self) as usize]
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}
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}
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impl From<Ratio> for u8 {
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fn from(variant: Ratio) -> Self {
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variant as _
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@ -136,31 +234,6 @@ impl From<Channels> for u8 {
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}
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}
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/// I2S Mode
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum Mode {
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Controller,
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Peripheral,
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}
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// /// Master clock generator frequency.
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// #[derive(Debug, Eq, PartialEq, Clone, Copy)]
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// pub enum MckFreq {
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// _32MDiv8 = 0x20000000,
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// _32MDiv10 = 0x18000000,
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// _32MDiv11 = 0x16000000,
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// _32MDiv15 = 0x11000000,
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// _32MDiv16 = 0x10000000,
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// _32MDiv21 = 0x0C000000,
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// _32MDiv23 = 0x0B000000,
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// _32MDiv30 = 0x08800000,
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// _32MDiv31 = 0x08400000,
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// _32MDiv32 = 0x08000000,
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// _32MDiv42 = 0x06000000,
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// _32MDiv63 = 0x04100000,
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// _32MDiv125 = 0x020C0000,
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// }
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/// Interface to the UARTE peripheral using EasyDMA to offload the transmission and reception workload.
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///
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/// For more details about EasyDMA, consult the module documentation.
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@ -185,7 +258,7 @@ impl<'d, T: Instance> I2S<'d, T> {
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/// Create a new I2S
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pub fn new(
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i2s: impl Peripheral<P = T> + 'd,
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// irq: impl Peripheral<P = T::Interrupt> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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mck: impl Peripheral<P = impl GpioPin> + 'd,
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sck: impl Peripheral<P = impl GpioPin> + 'd,
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lrck: impl Peripheral<P = impl GpioPin> + 'd,
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@ -196,7 +269,7 @@ impl<'d, T: Instance> I2S<'d, T> {
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into_ref!(mck, sck, lrck, sdin, sdout);
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Self::new_inner(
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i2s,
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// irq,
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irq,
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mck.map_into(),
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sck.map_into(),
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lrck.map_into(),
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@ -208,7 +281,7 @@ impl<'d, T: Instance> I2S<'d, T> {
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fn new_inner(
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i2s: impl Peripheral<P = T> + 'd,
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// irq: impl Peripheral<P = T::Interrupt> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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mck: PeripheralRef<'d, AnyPin>,
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sck: PeripheralRef<'d, AnyPin>,
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lrck: PeripheralRef<'d, AnyPin>,
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@ -216,36 +289,12 @@ impl<'d, T: Instance> I2S<'d, T> {
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sdout: PeripheralRef<'d, AnyPin>,
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config: Config,
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) -> Self {
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into_ref!(i2s, /* irq, */ mck, sck, lrck, sdin, sdout);
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into_ref!(i2s, irq, mck, sck, lrck, sdin, sdout);
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let r = T::regs();
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Self::apply_config(&r.config, &config);
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r.psel.mck.write(|w| {
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unsafe { w.bits(mck.psel_bits()) };
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w.connect().connected()
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});
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r.psel.sck.write(|w| {
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unsafe { w.bits(sck.psel_bits()) };
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w.connect().connected()
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});
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r.psel.lrck.write(|w| {
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unsafe { w.bits(lrck.psel_bits()) };
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w.connect().connected()
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});
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r.psel.sdin.write(|w| {
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unsafe { w.bits(sdin.psel_bits()) };
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w.connect().connected()
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});
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r.psel.sdout.write(|w| {
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unsafe { w.bits(sdout.psel_bits()) };
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w.connect().connected()
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});
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Self::select_pins(&r.psel, mck, sck, lrck, sdin, sdout);
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Self::setup_interrupt(irq, r);
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r.enable.write(|w| w.enable().enabled());
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@ -322,19 +371,87 @@ impl<'d, T: Instance> I2S<'d, T> {
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self.input.rx(buffer).await
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}
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fn apply_config(c: &CONFIG, config: &Config) {
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// TODO support slave too
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c.mcken.write(|w| w.mcken().enabled());
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c.mckfreq.write(|w| w.mckfreq()._32mdiv16());
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c.mode.write(|w| w.mode().master());
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fn on_interrupt(_: *mut ()) {
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let r = T::regs();
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let s = T::state();
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if r.events_txptrupd.read().bits() != 0 {
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s.tx_waker.wake();
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r.intenclr.write(|w| w.txptrupd().clear());
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}
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if r.events_rxptrupd.read().bits() != 0 {
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s.rx_waker.wake();
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r.intenclr.write(|w| w.rxptrupd().clear());
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}
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}
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fn apply_config(c: &CONFIG, config: &Config) {
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match config.mode {
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Mode::Master { freq, ratio } => {
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c.mode.write(|w| w.mode().master());
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c.mcken.write(|w| w.mcken().enabled());
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c.mckfreq
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.write(|w| unsafe { w.mckfreq().bits(freq.to_register_value()) });
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c.ratio.write(|w| unsafe { w.ratio().bits(ratio.into()) });
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}
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Mode::Slave => {
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c.mode.write(|w| w.mode().slave());
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}
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};
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c.ratio.write(|w| unsafe { w.ratio().bits(config.ratio.into()) });
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c.swidth.write(|w| unsafe { w.swidth().bits(config.swidth.into()) });
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c.align.write(|w| w.align().bit(config.align.into()));
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c.format.write(|w| w.format().bit(config.format.into()));
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c.channels
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.write(|w| unsafe { w.channels().bits(config.channels.into()) });
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}
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fn select_pins(
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psel: &PSEL,
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mck: PeripheralRef<'d, AnyPin>,
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sck: PeripheralRef<'d, AnyPin>,
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lrck: PeripheralRef<'d, AnyPin>,
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sdin: PeripheralRef<'d, AnyPin>,
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sdout: PeripheralRef<'d, AnyPin>,
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) {
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psel.mck.write(|w| {
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unsafe { w.bits(mck.psel_bits()) };
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w.connect().connected()
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});
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psel.sck.write(|w| {
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unsafe { w.bits(sck.psel_bits()) };
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w.connect().connected()
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});
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psel.lrck.write(|w| {
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unsafe { w.bits(lrck.psel_bits()) };
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w.connect().connected()
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});
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psel.sdin.write(|w| {
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unsafe { w.bits(sdin.psel_bits()) };
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w.connect().connected()
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});
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psel.sdout.write(|w| {
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unsafe { w.bits(sdout.psel_bits()) };
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w.connect().connected()
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});
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}
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fn setup_interrupt(irq: PeripheralRef<'d, T::Interrupt>, r: &RegisterBlock) {
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irq.set_handler(Self::on_interrupt);
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irq.set_priority(Priority::P1); // TODO review priorities
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irq.unpend();
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irq.enable();
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r.intenclr.write(|w| w.rxptrupd().clear());
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r.intenclr.write(|w| w.txptrupd().clear());
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r.events_rxptrupd.reset();
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r.events_txptrupd.reset();
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}
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}
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impl<'d, T: Instance> I2sOutput<'d, T> {
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@ -360,15 +477,40 @@ impl<'d, T: Instance> I2sOutput<'d, T> {
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}
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let r = T::regs();
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let _s = T::state();
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let s = T::state();
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// TODO we can not progress until the last buffer written in TXD.PTR
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// has started the transmission.
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// We can use some sync primitive from `embassy-sync`.
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let drop = OnDrop::new(move || {
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trace!("write drop: stopping");
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r.intenclr.write(|w| w.txptrupd().clear());
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r.events_txptrupd.reset();
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r.config.txen.write(|w| w.txen().disabled());
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// TX is stopped almost instantly, spinning is fine.
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while r.events_txptrupd.read().bits() == 0 {}
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trace!("write drop: stopped");
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});
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r.txd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
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r.rxtxd.maxcnt.write(|w| unsafe { w.bits(maxcnt) });
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r.intenset.write(|w| w.txptrupd().set());
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compiler_fence(Ordering::SeqCst);
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poll_fn(|cx| {
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s.tx_waker.register(cx.waker());
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if r.events_txptrupd.read().bits() != 0 {
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Poll::Ready(())
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} else {
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Poll::Pending
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}
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})
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.await;
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compiler_fence(Ordering::SeqCst);
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drop.defuse();
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Ok(())
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}
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}
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@ -451,23 +593,19 @@ impl Buffer for &[i32] {
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}
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pub(crate) mod sealed {
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use core::sync::atomic::AtomicU8;
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use embassy_sync::waitqueue::AtomicWaker;
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//use super::*;
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pub struct State {
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pub input_waker: AtomicWaker,
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pub output_waker: AtomicWaker,
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pub buffers_refcount: AtomicU8,
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pub rx_waker: AtomicWaker,
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pub tx_waker: AtomicWaker,
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}
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impl State {
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pub const fn new() -> Self {
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Self {
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input_waker: AtomicWaker::new(),
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output_waker: AtomicWaker::new(),
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buffers_refcount: AtomicU8::new(0),
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rx_waker: AtomicWaker::new(),
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tx_waker: AtomicWaker::new(),
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}
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}
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}
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@ -74,7 +74,7 @@ pub mod buffered_uarte;
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pub mod gpio;
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#[cfg(feature = "gpiote")]
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pub mod gpiote;
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#[cfg(any(feature = "nrf52832", feature = "nrf52833", feature = "nrf52840",))]
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#[cfg(any(feature = "nrf52832", feature = "nrf52833", feature = "nrf52840"))]
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pub mod i2s;
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#[cfg(not(any(feature = "_nrf5340", feature = "_nrf9160")))]
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pub mod nvmc;
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