Add timer/rtc impl macro
This commit is contained in:
Thales Fragoso
parent
e49e3723a8
commit
13698d58e4
@ -186,6 +186,10 @@ for chip in chips.values():
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if func := funcs.get(f'{name}_D7'):
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f.write(f'impl_sdmmc_pin!({name}, D7Pin, {pin}, {func});')
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if block_name == 'TimGp16':
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if re.match('TIM[2345]$', name):
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f.write(f'impl_timer!({name});')
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if block_mod == 'exti':
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for irq in chip['interrupts']:
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if re.match('EXTI', irq):
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@ -1,10 +1,11 @@
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#![macro_use]
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use core::cell::Cell;
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use core::convert::TryInto;
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use core::sync::atomic::{compiler_fence, AtomicU32, Ordering};
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use embassy::interrupt::InterruptExt;
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use embassy::time::{Clock, TICKS_PER_SECOND};
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use embassy::util::AtomicWaker;
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use crate::interrupt::{CriticalSection, Interrupt, Mutex};
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use crate::pac::timer::TimGp16;
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@ -339,247 +340,22 @@ pub(crate) mod sealed {
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type Interrupt: Interrupt;
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fn inner() -> TimerInner;
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fn state() -> &'static AtomicWaker;
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}
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}
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pub trait Instance: sealed::Instance + Sized + 'static {}
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/*
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#[allow(unused_macros)]
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macro_rules! impl_timer {
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($module:ident: ($TYPE:ident, $INT:ident, $apbenr:ident, $enrbit:expr, $apbrstr:ident, $rstrbit:expr, $ppre:ident, $pclk: ident), 3) => {
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mod $module {
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use super::*;
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($inst:ident) => {
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impl crate::rtc::sealed::Instance for peripherals::$inst {
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type Interrupt = interrupt::$inst;
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impl sealed::Instance for $TYPE {}
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impl Instance for $TYPE {
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type Interrupt = interrupt::$INT;
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fn set_compare(&self, n: usize, value: u16) {
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// NOTE(unsafe) these registers accept all the range of u16 values
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match n {
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0 => self.ccr1.write(|w| unsafe { w.bits(value.into()) }),
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1 => self.ccr2.write(|w| unsafe { w.bits(value.into()) }),
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2 => self.ccr3.write(|w| unsafe { w.bits(value.into()) }),
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3 => self.ccr4.write(|w| unsafe { w.bits(value.into()) }),
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_ => {}
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}
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}
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fn set_compare_interrupt(&self, n: usize, enable: bool) {
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if n > 3 {
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return;
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}
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let bit = n as u8 + 1;
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unsafe {
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if enable {
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bb::set(&self.dier, bit);
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} else {
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bb::clear(&self.dier, bit);
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}
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}
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}
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fn compare_interrupt_status(&self, n: usize) -> bool {
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let status = self.sr.read();
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match n {
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0 => status.cc1if().bit_is_set(),
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1 => status.cc2if().bit_is_set(),
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2 => status.cc3if().bit_is_set(),
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3 => status.cc4if().bit_is_set(),
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_ => false,
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}
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}
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fn compare_clear_flag(&self, n: usize) {
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if n > 3 {
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return;
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}
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let bit = n as u8 + 1;
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unsafe {
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bb::clear(&self.sr, bit);
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}
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}
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fn overflow_interrupt_status(&self) -> bool {
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self.sr.read().uif().bit_is_set()
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}
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fn overflow_clear_flag(&self) {
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unsafe {
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bb::clear(&self.sr, 0);
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}
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}
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fn set_psc_arr(&self, psc: u16, arr: u16) {
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// NOTE(unsafe) All u16 values are valid
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self.psc.write(|w| unsafe { w.bits(psc.into()) });
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self.arr.write(|w| unsafe { w.bits(arr.into()) });
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unsafe {
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// Set URS, generate update, clear URS
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bb::set(&self.cr1, 2);
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self.egr.write(|w| w.ug().set_bit());
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bb::clear(&self.cr1, 2);
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}
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}
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fn stop_and_reset(&self) {
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unsafe {
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bb::clear(&self.cr1, 0);
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}
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self.cnt.reset();
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}
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fn start(&self) {
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unsafe { bb::set(&self.cr1, 0) }
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}
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fn counter(&self) -> u16 {
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self.cnt.read().bits() as u16
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}
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fn ppre(clocks: &Clocks) -> u8 {
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clocks.$ppre()
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}
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fn pclk(clocks: &Clocks) -> u32 {
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clocks.$pclk().0
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}
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fn inner() -> crate::rtc::TimerInner {
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const INNER: crate::rtc::TimerInner = crate::rtc::TimerInner($inst);
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INNER
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}
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}
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};
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($module:ident: ($TYPE:ident, $INT:ident, $apbenr:ident, $enrbit:expr, $apbrstr:ident, $rstrbit:expr, $ppre:ident, $pclk: ident), 1) => {
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mod $module {
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use super::*;
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use crate::hal::pac::{$TYPE, RCC};
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impl sealed::Sealed for $TYPE {}
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impl Instance for $TYPE {
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type Interrupt = interrupt::$INT;
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const REAL_ALARM_COUNT: usize = 1;
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fn enable_clock(&self) {
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// NOTE(unsafe) It will only be used for atomic operations
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unsafe {
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let rcc = &*RCC::ptr();
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bb::set(&rcc.$apbenr, $enrbit);
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bb::set(&rcc.$apbrstr, $rstrbit);
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bb::clear(&rcc.$apbrstr, $rstrbit);
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}
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}
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fn set_compare(&self, n: usize, value: u16) {
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// NOTE(unsafe) these registers accept all the range of u16 values
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match n {
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0 => self.ccr1.write(|w| unsafe { w.bits(value.into()) }),
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1 => self.ccr2.write(|w| unsafe { w.bits(value.into()) }),
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_ => {}
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}
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}
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fn set_compare_interrupt(&self, n: usize, enable: bool) {
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if n > 1 {
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return;
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}
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let bit = n as u8 + 1;
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unsafe {
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if enable {
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bb::set(&self.dier, bit);
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} else {
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bb::clear(&self.dier, bit);
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}
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}
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}
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fn compare_interrupt_status(&self, n: usize) -> bool {
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let status = self.sr.read();
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match n {
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0 => status.cc1if().bit_is_set(),
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1 => status.cc2if().bit_is_set(),
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_ => false,
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}
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}
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fn compare_clear_flag(&self, n: usize) {
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if n > 1 {
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return;
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}
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let bit = n as u8 + 1;
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unsafe {
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bb::clear(&self.sr, bit);
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}
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}
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fn overflow_interrupt_status(&self) -> bool {
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self.sr.read().uif().bit_is_set()
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}
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fn overflow_clear_flag(&self) {
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unsafe {
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bb::clear(&self.sr, 0);
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}
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}
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fn set_psc_arr(&self, psc: u16, arr: u16) {
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// NOTE(unsafe) All u16 values are valid
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self.psc.write(|w| unsafe { w.bits(psc.into()) });
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self.arr.write(|w| unsafe { w.bits(arr.into()) });
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unsafe {
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// Set URS, generate update, clear URS
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bb::set(&self.cr1, 2);
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self.egr.write(|w| w.ug().set_bit());
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bb::clear(&self.cr1, 2);
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}
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}
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fn stop_and_reset(&self) {
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unsafe {
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bb::clear(&self.cr1, 0);
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}
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self.cnt.reset();
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}
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fn start(&self) {
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unsafe { bb::set(&self.cr1, 0) }
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}
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fn counter(&self) -> u16 {
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self.cnt.read().bits() as u16
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}
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fn ppre(clocks: &Clocks) -> u8 {
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clocks.$ppre()
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}
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fn pclk(clocks: &Clocks) -> u32 {
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clocks.$pclk().0
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}
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}
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}
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impl crate::rtc::Instance for peripherals::$inst {}
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};
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}
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*/
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/*
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impl_timer!(tim2: (TIM2, TIM2, apb1enr, 0, apb1rstr, 0, ppre1, pclk1), 3);
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impl_timer!(tim3: (TIM3, TIM3, apb1enr, 1, apb1rstr, 1, ppre1, pclk1), 3);
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impl_timer!(tim4: (TIM4, TIM4, apb1enr, 2, apb1rstr, 2, ppre1, pclk1), 3);
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impl_timer!(tim5: (TIM5, TIM5, apb1enr, 3, apb1rstr, 3, ppre1, pclk1), 3);
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impl_timer!(tim9: (TIM9, TIM1_BRK_TIM9, apb2enr, 16, apb2rstr, 16, ppre2, pclk2), 1);
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#[cfg(not(any(feature = "stm32f401", feature = "stm32f410", feature = "stm32f411")))]
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impl_timer!(tim12: (TIM12, TIM8_BRK_TIM12, apb1enr, 6, apb1rstr, 6, ppre1, pclk1), 1);
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*/
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