Introduces split on the nRF Uarte
A new `split` method is introduced such that the Uarte tx and rx can be used from separate tasks. An MPSC is used to illustrate how data may be passed between these tasks.
This commit is contained in:
huntc
@ -54,6 +54,20 @@ impl Default for Config {
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/// Interface to the UARTE peripheral
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pub struct Uarte<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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tx: UarteTx<'d, T>,
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rx: UarteRx<'d, T>,
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}
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/// Transmitter interface to the UARTE peripheral obtained
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/// via [Uarte]::split.
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pub struct UarteTx<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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}
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/// Receiver interface to the UARTE peripheral obtained
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/// via [Uarte]::split.
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pub struct UarteRx<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: Instance> Uarte<'d, T> {
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@ -121,9 +135,18 @@ impl<'d, T: Instance> Uarte<'d, T> {
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Self {
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phantom: PhantomData,
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tx: UarteTx::new(),
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rx: UarteRx::new(),
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}
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}
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/// Split the Uarte into a transmitter and receiver, which is
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/// particuarly useful when having two tasks correlating to
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/// transmitting and receiving.
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pub fn split(self) -> (UarteTx<'d, T>, UarteRx<'d, T>) {
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(self.tx, self.rx)
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}
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fn on_interrupt(_: *mut ()) {
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let r = T::regs();
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let s = T::state();
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@ -139,34 +162,33 @@ impl<'d, T: Instance> Uarte<'d, T> {
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}
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}
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impl<'a, T: Instance> Drop for Uarte<'a, T> {
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fn drop(&mut self) {
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info!("uarte drop");
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impl<'d, T: Instance> Read for Uarte<'d, T> {
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#[rustfmt::skip]
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type ReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), TraitError>> + 'a;
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let r = T::regs();
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let did_stoprx = r.events_rxstarted.read().bits() != 0;
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let did_stoptx = r.events_txstarted.read().bits() != 0;
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info!("did_stoprx {} did_stoptx {}", did_stoprx, did_stoptx);
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// Wait for rxto or txstopped, if needed.
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while (did_stoprx && r.events_rxto.read().bits() == 0)
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|| (did_stoptx && r.events_txstopped.read().bits() == 0)
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{}
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// Finally we can disable!
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r.enable.write(|w| w.enable().disabled());
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gpio::deconfigure_pin(r.psel.rxd.read().bits());
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gpio::deconfigure_pin(r.psel.txd.read().bits());
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gpio::deconfigure_pin(r.psel.rts.read().bits());
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gpio::deconfigure_pin(r.psel.cts.read().bits());
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info!("uarte drop: done");
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fn read<'a>(&'a mut self, rx_buffer: &'a mut [u8]) -> Self::ReadFuture<'a> {
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self.rx.read(rx_buffer)
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}
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}
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impl<'d, T: Instance> Read for Uarte<'d, T> {
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impl<'d, T: Instance> Write for Uarte<'d, T> {
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#[rustfmt::skip]
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type WriteFuture<'a> where Self: 'a = impl Future<Output = Result<(), TraitError>> + 'a;
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fn write<'a>(&'a mut self, tx_buffer: &'a [u8]) -> Self::WriteFuture<'a> {
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self.tx.write(tx_buffer)
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}
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}
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impl<'d, T: Instance> UarteTx<'d, T> {
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pub fn new() -> Self {
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Self {
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phantom: PhantomData,
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}
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}
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}
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impl<'d, T: Instance> Read for UarteTx<'d, T> {
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#[rustfmt::skip]
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type ReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), TraitError>> + 'a;
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@ -220,7 +242,7 @@ impl<'d, T: Instance> Read for Uarte<'d, T> {
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}
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}
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impl<'d, T: Instance> Write for Uarte<'d, T> {
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impl<'d, T: Instance> Write for UarteTx<'d, T> {
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#[rustfmt::skip]
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type WriteFuture<'a> where Self: 'a = impl Future<Output = Result<(), TraitError>> + 'a;
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@ -275,6 +297,164 @@ impl<'d, T: Instance> Write for Uarte<'d, T> {
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}
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}
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impl<'a, T: Instance> Drop for UarteTx<'a, T> {
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fn drop(&mut self) {
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info!("uarte tx drop");
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let r = T::regs();
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let did_stoptx = r.events_txstarted.read().bits() != 0;
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info!("did_stoptx {}", did_stoptx);
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// Wait for txstopped, if needed.
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while did_stoptx && r.events_txstopped.read().bits() == 0 {}
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info!("uarte txdrop: done");
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}
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}
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impl<'d, T: Instance> UarteRx<'d, T> {
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pub fn new() -> Self {
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Self {
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phantom: PhantomData,
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}
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}
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}
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impl<'d, T: Instance> Read for UarteRx<'d, T> {
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#[rustfmt::skip]
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type ReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), TraitError>> + 'a;
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fn read<'a>(&'a mut self, rx_buffer: &'a mut [u8]) -> Self::ReadFuture<'a> {
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async move {
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let ptr = rx_buffer.as_ptr();
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let len = rx_buffer.len();
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assert!(len <= EASY_DMA_SIZE);
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let r = T::regs();
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let s = T::state();
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let drop = OnDrop::new(move || {
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info!("read drop: stopping");
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r.intenclr.write(|w| w.endrx().clear());
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r.events_rxto.reset();
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r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
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while r.events_endrx.read().bits() == 0 {}
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info!("read drop: stopped");
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});
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r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
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r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
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r.events_endrx.reset();
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r.intenset.write(|w| w.endrx().set());
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compiler_fence(Ordering::SeqCst);
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trace!("startrx");
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r.tasks_startrx.write(|w| unsafe { w.bits(1) });
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poll_fn(|cx| {
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s.endrx_waker.register(cx.waker());
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if r.events_endrx.read().bits() != 0 {
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return Poll::Ready(());
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}
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Poll::Pending
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})
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.await;
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compiler_fence(Ordering::SeqCst);
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r.events_rxstarted.reset();
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drop.defuse();
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Ok(())
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}
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}
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}
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impl<'d, T: Instance> Write for UarteRx<'d, T> {
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#[rustfmt::skip]
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type WriteFuture<'a> where Self: 'a = impl Future<Output = Result<(), TraitError>> + 'a;
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fn write<'a>(&'a mut self, tx_buffer: &'a [u8]) -> Self::WriteFuture<'a> {
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async move {
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let ptr = tx_buffer.as_ptr();
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let len = tx_buffer.len();
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assert!(len <= EASY_DMA_SIZE);
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// TODO: panic if buffer is not in SRAM
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let r = T::regs();
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let s = T::state();
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let drop = OnDrop::new(move || {
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info!("write drop: stopping");
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r.intenclr.write(|w| w.endtx().clear());
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r.events_txstopped.reset();
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r.tasks_stoptx.write(|w| unsafe { w.bits(1) });
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// TX is stopped almost instantly, spinning is fine.
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while r.events_endtx.read().bits() == 0 {}
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info!("write drop: stopped");
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});
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r.txd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
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r.txd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
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r.events_endtx.reset();
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r.intenset.write(|w| w.endtx().set());
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compiler_fence(Ordering::SeqCst);
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trace!("starttx");
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r.tasks_starttx.write(|w| unsafe { w.bits(1) });
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poll_fn(|cx| {
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s.endtx_waker.register(cx.waker());
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if r.events_endtx.read().bits() != 0 {
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return Poll::Ready(());
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}
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Poll::Pending
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})
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.await;
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compiler_fence(Ordering::SeqCst);
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r.events_txstarted.reset();
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drop.defuse();
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Ok(())
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}
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}
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}
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impl<'a, T: Instance> Drop for UarteRx<'a, T> {
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fn drop(&mut self) {
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info!("uarte rx drop");
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let r = T::regs();
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let did_stoprx = r.events_rxstarted.read().bits() != 0;
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info!("did_stoprx {}", did_stoprx);
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// Wait for rxto, if needed.
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while did_stoprx && r.events_rxto.read().bits() == 0 {}
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// Finally we can disable, and we do so for the peripheral
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// i.e. not just rx concerns.
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r.enable.write(|w| w.enable().disabled());
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gpio::deconfigure_pin(r.psel.rxd.read().bits());
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gpio::deconfigure_pin(r.psel.txd.read().bits());
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gpio::deconfigure_pin(r.psel.rts.read().bits());
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gpio::deconfigure_pin(r.psel.cts.read().bits());
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info!("uarte drop: done");
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}
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}
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#[cfg(not(any(feature = "_nrf9160", feature = "nrf5340")))]
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pub(in crate) fn apply_workaround_for_enable_anomaly(_r: &crate::pac::uarte0::RegisterBlock) {
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// Do nothing
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