rp: remove take!, add bind_interrupts!
This commit is contained in:
pennae
@ -3,7 +3,7 @@ use core::slice;
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use core::task::Poll;
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use atomic_polyfill::{AtomicU8, Ordering};
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use embassy_cortex_m::interrupt::{Interrupt, InterruptExt};
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use embassy_cortex_m::interrupt::{self, Binding, Interrupt, InterruptExt};
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use embassy_hal_common::atomic_ring_buffer::RingBuffer;
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use embassy_sync::waitqueue::AtomicWaker;
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use embassy_time::{Duration, Timer};
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@ -52,7 +52,7 @@ pub struct BufferedUartTx<'d, T: Instance> {
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}
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pub(crate) fn init_buffers<'d, T: Instance + 'd>(
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irq: PeripheralRef<'d, T::Interrupt>,
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_irq: impl Binding<T::Interrupt, BufferedInterruptHandler<T>>,
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tx_buffer: &'d mut [u8],
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rx_buffer: &'d mut [u8],
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) {
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@ -79,24 +79,23 @@ pub(crate) fn init_buffers<'d, T: Instance + 'd>(
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w.set_rtim(true);
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w.set_txim(true);
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});
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};
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irq.set_handler(on_interrupt::<T>);
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irq.unpend();
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irq.enable();
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T::Interrupt::steal().unpend();
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T::Interrupt::steal().enable();
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};
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}
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impl<'d, T: Instance> BufferedUart<'d, T> {
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pub fn new(
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_uart: impl Peripheral<P = T> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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irq: impl Binding<T::Interrupt, BufferedInterruptHandler<T>>,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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tx_buffer: &'d mut [u8],
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rx_buffer: &'d mut [u8],
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config: Config,
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) -> Self {
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into_ref!(irq, tx, rx);
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into_ref!(tx, rx);
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super::Uart::<'d, T, Async>::init(Some(tx.map_into()), Some(rx.map_into()), None, None, config);
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init_buffers::<T>(irq, tx_buffer, rx_buffer);
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@ -109,7 +108,7 @@ impl<'d, T: Instance> BufferedUart<'d, T> {
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pub fn new_with_rtscts(
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_uart: impl Peripheral<P = T> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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irq: impl Binding<T::Interrupt, BufferedInterruptHandler<T>>,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
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@ -118,7 +117,7 @@ impl<'d, T: Instance> BufferedUart<'d, T> {
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rx_buffer: &'d mut [u8],
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config: Config,
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) -> Self {
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into_ref!(irq, tx, rx, cts, rts);
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into_ref!(tx, rx, cts, rts);
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super::Uart::<'d, T, Async>::init(
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Some(tx.map_into()),
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@ -163,12 +162,12 @@ impl<'d, T: Instance> BufferedUart<'d, T> {
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impl<'d, T: Instance> BufferedUartRx<'d, T> {
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pub fn new(
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_uart: impl Peripheral<P = T> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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irq: impl Binding<T::Interrupt, BufferedInterruptHandler<T>>,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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rx_buffer: &'d mut [u8],
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config: Config,
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) -> Self {
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into_ref!(irq, rx);
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into_ref!(rx);
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super::Uart::<'d, T, Async>::init(None, Some(rx.map_into()), None, None, config);
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init_buffers::<T>(irq, &mut [], rx_buffer);
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@ -178,13 +177,13 @@ impl<'d, T: Instance> BufferedUartRx<'d, T> {
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pub fn new_with_rts(
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_uart: impl Peripheral<P = T> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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irq: impl Binding<T::Interrupt, BufferedInterruptHandler<T>>,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
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rx_buffer: &'d mut [u8],
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config: Config,
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) -> Self {
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into_ref!(irq, rx, rts);
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into_ref!(rx, rts);
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super::Uart::<'d, T, Async>::init(None, Some(rx.map_into()), Some(rts.map_into()), None, config);
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init_buffers::<T>(irq, &mut [], rx_buffer);
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@ -312,12 +311,12 @@ impl<'d, T: Instance> BufferedUartRx<'d, T> {
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impl<'d, T: Instance> BufferedUartTx<'d, T> {
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pub fn new(
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_uart: impl Peripheral<P = T> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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irq: impl Binding<T::Interrupt, BufferedInterruptHandler<T>>,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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tx_buffer: &'d mut [u8],
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config: Config,
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) -> Self {
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into_ref!(irq, tx);
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into_ref!(tx);
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super::Uart::<'d, T, Async>::init(Some(tx.map_into()), None, None, None, config);
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init_buffers::<T>(irq, tx_buffer, &mut []);
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@ -327,13 +326,13 @@ impl<'d, T: Instance> BufferedUartTx<'d, T> {
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pub fn new_with_cts(
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_uart: impl Peripheral<P = T> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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irq: impl Binding<T::Interrupt, BufferedInterruptHandler<T>>,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
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tx_buffer: &'d mut [u8],
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config: Config,
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) -> Self {
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into_ref!(irq, tx, cts);
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into_ref!(tx, cts);
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super::Uart::<'d, T, Async>::init(Some(tx.map_into()), None, None, Some(cts.map_into()), config);
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init_buffers::<T>(irq, tx_buffer, &mut []);
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@ -482,97 +481,107 @@ impl<'d, T: Instance> Drop for BufferedUartTx<'d, T> {
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}
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}
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pub(crate) unsafe fn on_interrupt<T: Instance>(_: *mut ()) {
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let r = T::regs();
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let s = T::buffered_state();
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pub struct BufferedInterruptHandler<T: Instance> {
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_uart: PhantomData<T>,
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}
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unsafe {
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// Clear TX and error interrupt flags
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// RX interrupt flags are cleared by reading from the FIFO.
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let ris = r.uartris().read();
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r.uarticr().write(|w| {
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w.set_txic(ris.txris());
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w.set_feic(ris.feris());
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w.set_peic(ris.peris());
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w.set_beic(ris.beris());
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w.set_oeic(ris.oeris());
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});
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trace!("on_interrupt ris={:#X}", ris.0);
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// Errors
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if ris.feris() {
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warn!("Framing error");
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}
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if ris.peris() {
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warn!("Parity error");
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}
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if ris.beris() {
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warn!("Break error");
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}
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if ris.oeris() {
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warn!("Overrun error");
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impl<T: Instance> interrupt::Handler<T::Interrupt> for BufferedInterruptHandler<T> {
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unsafe fn on_interrupt() {
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let r = T::regs();
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if r.uartdmacr().read().rxdmae() {
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return;
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}
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// RX
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let mut rx_writer = s.rx_buf.writer();
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let rx_buf = rx_writer.push_slice();
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let mut n_read = 0;
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let mut error = false;
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for rx_byte in rx_buf {
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if r.uartfr().read().rxfe() {
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break;
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}
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let dr = r.uartdr().read();
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if (dr.0 >> 8) != 0 {
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s.rx_error.fetch_or((dr.0 >> 8) as u8, Ordering::Relaxed);
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error = true;
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// only fill the buffer with valid characters. the current character is fine
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// if the error is an overrun, but if we add it to the buffer we'll report
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// the overrun one character too late. drop it instead and pretend we were
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// a bit slower at draining the rx fifo than we actually were.
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// this is consistent with blocking uart error reporting.
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break;
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}
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*rx_byte = dr.data();
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n_read += 1;
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}
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if n_read > 0 {
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rx_writer.push_done(n_read);
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s.rx_waker.wake();
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} else if error {
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s.rx_waker.wake();
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}
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// Disable any further RX interrupts when the buffer becomes full or
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// errors have occurred. This lets us buffer additional errors in the
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// fifo without needing more error storage locations, and most applications
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// will want to do a full reset of their uart state anyway once an error
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// has happened.
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if s.rx_buf.is_full() || error {
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r.uartimsc().write_clear(|w| {
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w.set_rxim(true);
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w.set_rtim(true);
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let s = T::buffered_state();
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unsafe {
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// Clear TX and error interrupt flags
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// RX interrupt flags are cleared by reading from the FIFO.
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let ris = r.uartris().read();
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r.uarticr().write(|w| {
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w.set_txic(ris.txris());
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w.set_feic(ris.feris());
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w.set_peic(ris.peris());
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w.set_beic(ris.beris());
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w.set_oeic(ris.oeris());
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});
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}
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// TX
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let mut tx_reader = s.tx_buf.reader();
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let tx_buf = tx_reader.pop_slice();
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let mut n_written = 0;
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for tx_byte in tx_buf.iter_mut() {
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if r.uartfr().read().txff() {
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break;
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trace!("on_interrupt ris={:#X}", ris.0);
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// Errors
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if ris.feris() {
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warn!("Framing error");
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}
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r.uartdr().write(|w| w.set_data(*tx_byte));
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n_written += 1;
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if ris.peris() {
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warn!("Parity error");
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}
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if ris.beris() {
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warn!("Break error");
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}
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if ris.oeris() {
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warn!("Overrun error");
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}
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// RX
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let mut rx_writer = s.rx_buf.writer();
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let rx_buf = rx_writer.push_slice();
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let mut n_read = 0;
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let mut error = false;
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for rx_byte in rx_buf {
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if r.uartfr().read().rxfe() {
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break;
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}
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let dr = r.uartdr().read();
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if (dr.0 >> 8) != 0 {
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s.rx_error.fetch_or((dr.0 >> 8) as u8, Ordering::Relaxed);
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error = true;
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// only fill the buffer with valid characters. the current character is fine
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// if the error is an overrun, but if we add it to the buffer we'll report
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// the overrun one character too late. drop it instead and pretend we were
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// a bit slower at draining the rx fifo than we actually were.
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// this is consistent with blocking uart error reporting.
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break;
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}
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*rx_byte = dr.data();
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n_read += 1;
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}
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if n_read > 0 {
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rx_writer.push_done(n_read);
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s.rx_waker.wake();
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} else if error {
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s.rx_waker.wake();
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}
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// Disable any further RX interrupts when the buffer becomes full or
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// errors have occurred. This lets us buffer additional errors in the
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// fifo without needing more error storage locations, and most applications
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// will want to do a full reset of their uart state anyway once an error
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// has happened.
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if s.rx_buf.is_full() || error {
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r.uartimsc().write_clear(|w| {
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w.set_rxim(true);
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w.set_rtim(true);
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});
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}
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// TX
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let mut tx_reader = s.tx_buf.reader();
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let tx_buf = tx_reader.pop_slice();
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let mut n_written = 0;
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for tx_byte in tx_buf.iter_mut() {
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if r.uartfr().read().txff() {
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break;
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}
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r.uartdr().write(|w| w.set_data(*tx_byte));
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n_written += 1;
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}
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if n_written > 0 {
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tx_reader.pop_done(n_written);
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s.tx_waker.wake();
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}
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// The TX interrupt only triggers once when the FIFO threshold is
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// crossed. No need to disable it when the buffer becomes empty
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// as it does re-trigger anymore once we have cleared it.
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}
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if n_written > 0 {
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tx_reader.pop_done(n_written);
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s.tx_waker.wake();
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}
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// The TX interrupt only triggers once when the FIFO threshold is
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// crossed. No need to disable it when the buffer becomes empty
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// as it does re-trigger anymore once we have cleared it.
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}
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}
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