From 14fa6c2760cd7468eda8ed4fe7142199714201bd Mon Sep 17 00:00:00 2001 From: Adam Greig Date: Mon, 6 Sep 2021 23:16:43 +0100 Subject: [PATCH] STM32H7: Ethernet: Disable RA in MAC filtering, fix order of MACA0 register writes. --- embassy-stm32/src/eth/v2/mod.rs | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/embassy-stm32/src/eth/v2/mod.rs b/embassy-stm32/src/eth/v2/mod.rs index a06c4cac..42eb0680 100644 --- a/embassy-stm32/src/eth/v2/mod.rs +++ b/embassy-stm32/src/eth/v2/mod.rs @@ -98,6 +98,10 @@ impl<'d, P: PHY, const TX: usize, const RX: usize> Ethernet<'d, P, TX, RX> { // TODO: Carrier sense ? ECRSFD }); + // Note: Writing to LR triggers synchronisation of both LR and HR into the MAC core, + // so the LR write must happen after the HR write. + mac.maca0hr() + .modify(|w| w.set_addrhi(u16::from(mac_addr[4]) | (u16::from(mac_addr[5]) << 8))); mac.maca0lr().write(|w| { w.set_addrlo( u32::from(mac_addr[0]) @@ -106,10 +110,7 @@ impl<'d, P: PHY, const TX: usize, const RX: usize> Ethernet<'d, P, TX, RX> { | (u32::from(mac_addr[3]) << 24), ) }); - mac.maca0hr() - .modify(|w| w.set_addrhi(u16::from(mac_addr[4]) | (u16::from(mac_addr[5]) << 8))); - mac.macpfr().modify(|w| w.set_ra(true)); mac.macqtx_fcr().modify(|w| w.set_pt(0x100)); mtl.mtlrx_qomr().modify(|w| w.set_rsf(true));