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Fix async write bug

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This commit is contained in:
Grant Miller 2022-03-14 18:04:31 -05:00
parent 064170fce0
commit 15c533fe2a
1 changed files with 3 additions and 4 deletions
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7
embassy-stm32/src/spi/mod.rs
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@ -418,10 +418,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
}); });
} }
// TODO: This is unnecessary in some versions because
// clearing SPE automatically clears the fifos
flush_rx_fifo(T::REGS);
let tx_request = self.txdma.request(); let tx_request = self.txdma.request();
let tx_dst = T::REGS.tx_ptr(); let tx_dst = T::REGS.tx_ptr();
unsafe { self.txdma.start_write(tx_request, data, tx_dst) } unsafe { self.txdma.start_write(tx_request, data, tx_dst) }
@ -440,6 +436,9 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
tx_f.await; tx_f.await;
// flush here otherwise `finish_dma` hangs waiting for the rx fifo to empty
flush_rx_fifo(T::REGS);
finish_dma(T::REGS); finish_dma(T::REGS);
Ok(()) Ok(())