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stm32/metapac: check GPIO RCC regs are always found.

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This commit is contained in:
Dario Nieuwenhuis 2021-08-19 23:51:53 +02:00
parent 2c992f7010
commit 174c51f097
4 changed files with 10 additions and 32 deletions
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12
embassy-stm32/src/rcc/f0/mod.rs
View File

@ -202,18 +202,6 @@ impl<'d> Rcc<'d> {
} }
pub unsafe fn init(config: Config) { pub unsafe fn init(config: Config) {
RCC.ahbenr().modify(|w| {
w.set_iopaen(true);
w.set_iopben(true);
w.set_iopcen(true);
w.set_iopden(true);
#[cfg(rcc_f0)]
w.set_iopeen(true);
w.set_iopfen(true);
});
let rcc = Rcc::new(<peripherals::RCC as embassy::util::Steal>::steal(), config); let rcc = Rcc::new(<peripherals::RCC as embassy::util::Steal>::steal(), config);
let clocks = rcc.freeze(); let clocks = rcc.freeze();
set_freqs(clocks); set_freqs(clocks);

10
embassy-stm32/src/rcc/l0/mod.rs
View File

@ -377,16 +377,6 @@ impl RccExt for RCC {
pub struct HSI48(()); pub struct HSI48(());
pub unsafe fn init(config: Config) { pub unsafe fn init(config: Config) {
let rcc = pac::RCC;
rcc.iopenr().write(|w| {
w.set_iopaen(true);
w.set_iopben(true);
w.set_iopcen(true);
w.set_iopden(true);
w.set_iopeen(true);
w.set_iophen(true);
});
let r = <peripherals::RCC as embassy::util::Steal>::steal(); let r = <peripherals::RCC as embassy::util::Steal>::steal();
let clocks = r.freeze(config); let clocks = r.freeze(config);
set_freqs(clocks); set_freqs(clocks);

2
stm32-data

@ -1 +1 @@
Subproject commit d3c03a41de925d07e26a5f6157eb85307692a651 Subproject commit 12be5f3da4ba38850d94ab865d2b920bd936300b

18
stm32-metapac-gen/src/lib.rs
View File

@ -117,11 +117,7 @@ impl BlockInfo {
} }
} }
fn find_reg_for_field<'c>( fn find_reg<'c>(rcc: &'c ir::IR, reg_regex: &str, field_name: &str) -> Option<(&'c str, &'c str)> {
rcc: &'c ir::IR,
reg_regex: &str,
field_name: &str,
) -> Option<(&'c str, &'c str)> {
let reg_regex = Regex::new(reg_regex).unwrap(); let reg_regex = Regex::new(reg_regex).unwrap();
for (name, fieldset) in &rcc.fieldsets { for (name, fieldset) in &rcc.fieldsets {
@ -426,16 +422,16 @@ pub fn gen(options: Options) {
// Workaround for clock registers being split on some chip families. Assume fields are // Workaround for clock registers being split on some chip families. Assume fields are
// named after peripheral and look for first field matching and use that register. // named after peripheral and look for first field matching and use that register.
let mut en = find_reg_for_field(&rcc, "^.+ENR\\d*$", &format!("{}EN", name)); let mut en = find_reg(&rcc, "^.+ENR\\d*$", &format!("{}EN", name));
let mut rst = find_reg_for_field(&rcc, "^.+RSTR\\d*$", &format!("{}RST", name)); let mut rst = find_reg(&rcc, "^.+RSTR\\d*$", &format!("{}RST", name));
if en.is_none() && name.ends_with("1") { if en.is_none() && name.ends_with("1") {
en = find_reg_for_field( en = find_reg(
&rcc, &rcc,
"^.+ENR\\d*$", "^.+ENR\\d*$",
&format!("{}EN", &name[..name.len() - 1]), &format!("{}EN", &name[..name.len() - 1]),
); );
rst = find_reg_for_field( rst = find_reg(
&rcc, &rcc,
"^.+RSTR\\d*$", "^.+RSTR\\d*$",
&format!("{}RST", &name[..name.len() - 1]), &format!("{}RST", &name[..name.len() - 1]),
@ -500,6 +496,10 @@ pub fn gen(options: Options) {
gpio_rcc_table.push(vec![reg]); gpio_rcc_table.push(vec![reg]);
} }
// We should always find GPIO RCC regs. If not, it means something
// is broken and GPIO won't work because it's not enabled.
assert!(!gpio_rcc_table.is_empty());
for (id, channel_info) in &core.dma_channels { for (id, channel_info) in &core.dma_channels {
let mut row = Vec::new(); let mut row = Vec::new();
let dma_peri = core.peripherals.get(&channel_info.dma).unwrap(); let dma_peri = core.peripherals.get(&channel_info.dma).unwrap();