Add SPI v3, fix up v2's af_num and remove extraneous Error enums.
This commit is contained in:
Bob McWhirter
parent
a4fd1282e9
commit
1872824d56
@ -2,6 +2,7 @@
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#[cfg_attr(feature = "_spi_v1", path = "v1.rs")]
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#[cfg_attr(feature = "_spi_v2", path = "v2.rs")]
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#[cfg_attr(feature = "_spi_v3", path = "v3.rs")]
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mod _version;
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pub use _version::*;
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@ -4,7 +4,7 @@ use crate::gpio::{AnyPin, Pin};
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use crate::pac::gpio::vals::{Afr, Moder};
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use crate::pac::gpio::Gpio;
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use crate::pac::spi;
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use crate::spi::{ByteOrder, Config, Instance, MisoPin, MosiPin, SckPin, WordSize};
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use crate::spi::{ByteOrder, Config, Instance, MisoPin, MosiPin, SckPin, WordSize, Error};
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use crate::time::Hertz;
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use core::marker::PhantomData;
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use embassy::util::Unborrow;
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@ -52,9 +52,9 @@ impl<'d, T: Instance> Spi<'d, T> {
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unborrow!(sck, mosi, miso);
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unsafe {
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Self::configure_pin(sck.block(), sck.pin() as _, sck.af());
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Self::configure_pin(mosi.block(), mosi.pin() as _, mosi.af());
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Self::configure_pin(miso.block(), miso.pin() as _, miso.af());
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Self::configure_pin(sck.block(), sck.pin() as _, sck.af_num());
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Self::configure_pin(mosi.block(), mosi.pin() as _, mosi.af_num());
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Self::configure_pin(miso.block(), miso.pin() as _, miso.af_num());
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}
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let sck = sck.degrade();
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@ -149,12 +149,6 @@ impl<'d, T: Instance> Drop for Spi<'d, T> {
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}
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}
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pub enum Error {
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Framing,
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Crc,
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Overrun,
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T> {
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type Error = Error;
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300
embassy-stm32/src/spi/v3.rs
Normal file
300
embassy-stm32/src/spi/v3.rs
Normal file
@ -0,0 +1,300 @@
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#![macro_use]
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use crate::gpio::{AnyPin, Pin};
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use crate::pac::gpio::vals::{Afr, Moder};
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use crate::pac::gpio::Gpio;
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use crate::pac::spi;
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use crate::spi::{ByteOrder, Config, Instance, MisoPin, MosiPin, SckPin, WordSize, Error};
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use crate::time::Hertz;
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use core::marker::PhantomData;
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use embassy::util::Unborrow;
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use embassy_extras::unborrow;
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pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
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impl WordSize {
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fn dsize(&self) -> u8 {
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match self {
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WordSize::EightBit => 0b0111,
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WordSize::SixteenBit => 0b1111,
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}
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}
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fn frxth(&self) -> spi::vals::Fthlv {
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match self {
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WordSize::EightBit => spi::vals::Fthlv::FOURFRAMES,
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WordSize::SixteenBit => spi::vals::Fthlv::EIGHTFRAMES,
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}
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}
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}
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pub struct Spi<'d, T: Instance> {
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//peri: T,
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sck: AnyPin,
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mosi: AnyPin,
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miso: AnyPin,
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: Instance> Spi<'d, T> {
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pub fn new<F>(
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pclk: Hertz,
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peri: impl Unborrow<Target=T> + 'd,
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sck: impl Unborrow<Target=impl SckPin<T>>,
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mosi: impl Unborrow<Target=impl MosiPin<T>>,
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miso: impl Unborrow<Target=impl MisoPin<T>>,
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freq: F,
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config: Config,
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) -> Self
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where
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F: Into<Hertz>,
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{
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unborrow!(peri);
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unborrow!(sck, mosi, miso);
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unsafe {
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Self::configure_pin(sck.block(), sck.pin() as _, sck.af_num());
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Self::configure_pin(mosi.block(), mosi.pin() as _, mosi.af_num());
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Self::configure_pin(miso.block(), miso.pin() as _, miso.af_num());
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}
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let sck = sck.degrade();
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let mosi = mosi.degrade();
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let miso = miso.degrade();
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unsafe {
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T::regs().cfg2().write(|w| {
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w.set_ssoe(false);
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w.set_cpha(
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match config.mode.phase == Phase::CaptureOnSecondTransition {
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true => spi::vals::Cpha::SECONDEDGE,
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false => spi::vals::Cpha::FIRSTEDGE,
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},
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);
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w.set_cpol(match config.mode.polarity == Polarity::IdleHigh {
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true => spi::vals::Cpol::IDLEHIGH,
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false => spi::vals::Cpol::IDLELOW,
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});
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});
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}
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let br = Self::compute_baud_rate(pclk, freq.into());
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unsafe {
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T::regs().cfg2().write(|w| {
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w.set_lsbfrst(match config.byte_order {
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ByteOrder::LsbFirst => spi::vals::Lsbfrst::LSBFIRST,
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ByteOrder::MsbFirst => spi::vals::Lsbfrst::MSBFIRST,
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});
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w.set_ssm(true);
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w.set_master(spi::vals::Master::MASTER);
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});
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T::regs().cfg1().write(|w| {
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w.set_crcen(false);
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w.set_mbr(spi::vals::Mbr(br));
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w.set_dsize(WordSize::EightBit.dsize());
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w.set_fthlv(WordSize::EightBit.frxth());
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});
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T::regs().cr1().write(|w| {
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w.set_ssi(true);
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w.set_spe(true);
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//w.set_bidimode(spi::vals::Bidimode::UNIDIRECTIONAL);
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});
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}
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Self {
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//peri,
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sck,
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mosi,
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miso,
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phantom: PhantomData,
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}
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}
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unsafe fn configure_pin(block: Gpio, pin: usize, af_num: u8) {
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let (afr, n_af) = if pin < 8 { (0, pin) } else { (1, pin - 8) };
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block.moder().modify(|w| w.set_moder(pin, Moder::ALTERNATE));
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block.afr(afr).modify(|w| w.set_afr(n_af, Afr(af_num)));
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}
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unsafe fn unconfigure_pin(block: Gpio, pin: usize) {
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block.moder().modify(|w| w.set_moder(pin, Moder::ANALOG));
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}
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fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> u8 {
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match clocks.0 / freq.0 {
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0 => unreachable!(),
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1..=2 => 0b000,
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3..=5 => 0b001,
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6..=11 => 0b010,
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12..=23 => 0b011,
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24..=39 => 0b100,
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40..=95 => 0b101,
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96..=191 => 0b110,
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_ => 0b111,
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}
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}
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fn set_word_size(word_size: WordSize) {
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unsafe {
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T::regs().cr1().write(|w| {
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w.set_spe(false);
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});
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T::regs().cfg1().write(|w| {
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w.set_dsize(word_size.dsize());
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w.set_fthlv(word_size.frxth());
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});
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T::regs().cr1().write(|w| {
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w.set_spe(true);
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});
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}
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}
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}
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impl<'d, T: Instance> Drop for Spi<'d, T> {
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fn drop(&mut self) {
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unsafe {
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Self::unconfigure_pin(self.sck.block(), self.sck.pin() as _);
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Self::unconfigure_pin(self.mosi.block(), self.mosi.pin() as _);
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Self::unconfigure_pin(self.miso.block(), self.miso.pin() as _);
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}
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T> {
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type Error = Error;
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fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
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Self::set_word_size(WordSize::EightBit);
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let regs = T::regs();
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for word in words.iter() {
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while unsafe { !regs.sr().read().txp() } {
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// spin
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}
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unsafe {
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//regs.dr().write(|reg| reg.0 = *word as u32);
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regs.txdr().write(|reg| reg.0 = *word as u32);
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}
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loop {
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let sr = unsafe { regs.sr().read() };
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if sr.tifre() {
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return Err(Error::Framing);
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}
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if sr.ovr() {
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return Err(Error::Overrun);
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}
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if sr.crce() {
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return Err(Error::Crc);
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}
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if !sr.txp() {
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// loop waiting for TXE
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}
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}
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}
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Ok(())
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> {
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type Error = Error;
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fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
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Self::set_word_size(WordSize::EightBit);
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let regs = T::regs();
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for word in words.iter_mut() {
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while unsafe { !regs.sr().read().txp() } {
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// spin
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}
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unsafe {
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regs.txdr().write(|reg| reg.0 = *word as u32);
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}
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while unsafe { ! regs.sr().read().rxp() } {
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// spin waiting for inbound to shift in.
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}
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*word = unsafe { regs.rxdr().read().0 as u8 };
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let sr = unsafe { regs.sr().read() };
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if sr.tifre() {
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return Err(Error::Framing);
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}
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if sr.ovr() {
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return Err(Error::Overrun);
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}
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if sr.crce() {
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return Err(Error::Crc);
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}
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}
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Ok(words)
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T> {
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type Error = Error;
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fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> {
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Self::set_word_size(WordSize::SixteenBit);
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let regs = T::regs();
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for word in words.iter() {
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while unsafe { !regs.sr().read().txp() } {
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// spin
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}
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unsafe {
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regs.txdr().write(|reg| reg.0 = *word as u32);
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}
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loop {
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let sr = unsafe { regs.sr().read() };
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if sr.tifre() {
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return Err(Error::Framing);
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}
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if sr.ovr() {
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return Err(Error::Overrun);
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}
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if sr.crce() {
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return Err(Error::Crc);
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}
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if !sr.txp() {
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// loop waiting for TXE
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}
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}
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}
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Ok(())
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T> {
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type Error = Error;
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fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> {
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Self::set_word_size(WordSize::SixteenBit);
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let regs = T::regs();
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for word in words.iter_mut() {
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while unsafe { !regs.sr().read().txp() } {
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// spin
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}
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unsafe {
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regs.txdr().write(|reg| reg.0 = *word as u32);
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}
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while unsafe { !regs.sr().read().rxp() } {
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// spin waiting for inbound to shift in.
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}
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*word = unsafe { regs.rxdr().read().0 as u16 };
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let sr = unsafe { regs.sr().read() };
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if sr.tifre() {
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return Err(Error::Framing);
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}
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if sr.ovr() {
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return Err(Error::Overrun);
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}
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if sr.crce() {
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return Err(Error::Crc);
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}
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}
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Ok(words)
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}
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}
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