Merge pull request #8 from danbev/test-ro-rw-constants
Rename REG_BUS_FEEDBEAD to REG_BUS_TEST_RO
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commit
193124bed1
14
src/lib.rs
14
src/lib.rs
@ -50,8 +50,8 @@ const REG_BUS_CTRL: u32 = 0x0;
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const REG_BUS_INTERRUPT: u32 = 0x04; // 16 bits - Interrupt status
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const REG_BUS_INTERRUPT: u32 = 0x04; // 16 bits - Interrupt status
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const REG_BUS_INTERRUPT_ENABLE: u32 = 0x06; // 16 bits - Interrupt mask
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const REG_BUS_INTERRUPT_ENABLE: u32 = 0x06; // 16 bits - Interrupt mask
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const REG_BUS_STATUS: u32 = 0x8;
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const REG_BUS_STATUS: u32 = 0x8;
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const REG_BUS_FEEDBEAD: u32 = 0x14;
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const REG_BUS_TEST_RO: u32 = 0x14;
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const REG_BUS_TEST: u32 = 0x18;
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const REG_BUS_TEST_RW: u32 = 0x18;
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const REG_BUS_RESP_DELAY: u32 = 0x1c;
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const REG_BUS_RESP_DELAY: u32 = 0x1c;
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// SPI_STATUS_REGISTER bits
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// SPI_STATUS_REGISTER bits
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@ -565,19 +565,19 @@ where
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Timer::after(Duration::from_millis(250)).await;
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Timer::after(Duration::from_millis(250)).await;
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info!("waiting for ping...");
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info!("waiting for ping...");
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while self.read32_swapped(REG_BUS_FEEDBEAD).await != FEEDBEAD {}
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while self.read32_swapped(REG_BUS_TEST_RO).await != FEEDBEAD {}
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info!("ping ok");
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info!("ping ok");
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self.write32_swapped(0x18, TEST_PATTERN).await;
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self.write32_swapped(REG_BUS_TEST_RW, TEST_PATTERN).await;
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let val = self.read32_swapped(REG_BUS_TEST).await;
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let val = self.read32_swapped(REG_BUS_TEST_RW).await;
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assert_eq!(val, TEST_PATTERN);
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assert_eq!(val, TEST_PATTERN);
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// 32bit, little endian.
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// 32bit, little endian.
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self.write32_swapped(REG_BUS_CTRL, 0x00010031).await;
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self.write32_swapped(REG_BUS_CTRL, 0x00010031).await;
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let val = self.read32(FUNC_BUS, REG_BUS_FEEDBEAD).await;
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let val = self.read32(FUNC_BUS, REG_BUS_TEST_RO).await;
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assert_eq!(val, FEEDBEAD);
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assert_eq!(val, FEEDBEAD);
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let val = self.read32(FUNC_BUS, REG_BUS_TEST).await;
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let val = self.read32(FUNC_BUS, REG_BUS_TEST_RW).await;
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assert_eq!(val, TEST_PATTERN);
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assert_eq!(val, TEST_PATTERN);
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// No response delay in any of the funcs.
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// No response delay in any of the funcs.
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