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nrf/qspi: add nrf53 support.

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This commit is contained in:
Dario Nieuwenhuis 2023-02-23 22:36:10 +01:00
parent 9eb65b11cb
commit 1955a225e8
3 changed files with 25 additions and 19 deletions
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5
embassy-nrf/src/chips/nrf5340_app.rs
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@ -250,6 +250,9 @@ embassy_hal_common::peripherals! {
TIMER1, TIMER1,
TIMER2, TIMER2,
// QSPI
QSPI,
// GPIOTE // GPIOTE
GPIOTE_CH0, GPIOTE_CH0,
GPIOTE_CH1, GPIOTE_CH1,
@ -393,6 +396,8 @@ impl_timer!(TIMER0, TIMER0, TIMER0);
impl_timer!(TIMER1, TIMER1, TIMER1); impl_timer!(TIMER1, TIMER1, TIMER1);
impl_timer!(TIMER2, TIMER2, TIMER2); impl_timer!(TIMER2, TIMER2, TIMER2);
impl_qspi!(QSPI, QSPI, QSPI);
impl_pin!(P0_00, 0, 0); impl_pin!(P0_00, 0, 0);
impl_pin!(P0_01, 0, 1); impl_pin!(P0_01, 0, 1);
#[cfg(feature = "nfc-pins-as-gpio")] #[cfg(feature = "nfc-pins-as-gpio")]

2
embassy-nrf/src/lib.rs
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@ -58,7 +58,7 @@ pub mod ppi;
pub mod pwm; pub mod pwm;
#[cfg(not(any(feature = "nrf51", feature = "_nrf9160", feature = "_nrf5340")))] #[cfg(not(any(feature = "nrf51", feature = "_nrf9160", feature = "_nrf5340")))]
pub mod qdec; pub mod qdec;
#[cfg(feature = "nrf52840")] #[cfg(any(feature = "nrf52840", feature = "_nrf5340-app"))]
pub mod qspi; pub mod qspi;
#[cfg(not(any(feature = "_nrf5340", feature = "_nrf9160")))] #[cfg(not(any(feature = "_nrf5340", feature = "_nrf9160")))]
pub mod rng; pub mod rng;

37
embassy-nrf/src/qspi.rs
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@ -133,25 +133,26 @@ impl<'d, T: Instance, const FLASH_SIZE: usize> Qspi<'d, T, FLASH_SIZE> {
let r = T::regs(); let r = T::regs();
sck.set_high(); macro_rules! config_pin {
csn.set_high(); ($pin:ident) => {
io0.set_high(); $pin.set_high();
io1.set_high(); $pin.conf().write(|w| {
io2.set_high(); w.dir().output();
io3.set_high(); w.drive().h0h1();
sck.conf().write(|w| w.dir().output().drive().h0h1()); #[cfg(feature = "_nrf5340-s")]
csn.conf().write(|w| w.dir().output().drive().h0h1()); w.mcusel().peripheral();
io0.conf().write(|w| w.dir().output().drive().h0h1()); w
io1.conf().write(|w| w.dir().output().drive().h0h1()); });
io2.conf().write(|w| w.dir().output().drive().h0h1()); r.psel.$pin.write(|w| unsafe { w.bits($pin.psel_bits()) });
io3.conf().write(|w| w.dir().output().drive().h0h1()); };
}
r.psel.sck.write(|w| unsafe { w.bits(sck.psel_bits()) }); config_pin!(sck);
r.psel.csn.write(|w| unsafe { w.bits(csn.psel_bits()) }); config_pin!(csn);
r.psel.io0.write(|w| unsafe { w.bits(io0.psel_bits()) }); config_pin!(io0);
r.psel.io1.write(|w| unsafe { w.bits(io1.psel_bits()) }); config_pin!(io1);
r.psel.io2.write(|w| unsafe { w.bits(io2.psel_bits()) }); config_pin!(io2);
r.psel.io3.write(|w| unsafe { w.bits(io3.psel_bits()) }); config_pin!(io3);
r.ifconfig0.write(|w| { r.ifconfig0.write(|w| {
w.addrmode().variant(config.address_mode); w.addrmode().variant(config.address_mode);