From 1a216958ac121befa7da6912db307516d1ddcb07 Mon Sep 17 00:00:00 2001
From: Ralf <jr-oss@gmx.net>
Date: Wed, 11 May 2022 20:54:09 +0200
Subject: [PATCH] stm32/rcc: Set flash prefetch buffer and half cycle access
 according to AHB clock prescaler

---
 embassy-stm32/src/rcc/f3.rs | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/embassy-stm32/src/rcc/f3.rs b/embassy-stm32/src/rcc/f3.rs
index ababc4f9..5a735144 100644
--- a/embassy-stm32/src/rcc/f3.rs
+++ b/embassy-stm32/src/rcc/f3.rs
@@ -93,7 +93,10 @@ pub(crate) unsafe fn init(config: Config) {
     assert!(pclk2 <= 72_000_000);
 
     // Set latency based on HCLK frquency
-    FLASH.acr().write(|w| {
+    // RM0316: "The prefetch buffer must be kept on when using a prescaler
+    // different from 1 on the AHB clock.", "Half-cycle access cannot be
+    // used when there is a prescaler different from 1 on the AHB clock"
+    FLASH.acr().modify(|w| {
         w.set_latency(if hclk <= 24_000_000 {
             Latency::WS0
         } else if hclk <= 48_000_000 {
@@ -101,6 +104,10 @@ pub(crate) unsafe fn init(config: Config) {
         } else {
             Latency::WS2
         });
+        if hpre_div != 1 {
+            w.set_hlfcya(false);
+            w.set_prftbe(true);
+        }
     });
 
     // Enable HSE