rp clock configuration
This commit is contained in:
Caleb Jamison
parent
79c60f4a7d
commit
1a96eae22c
@ -2,10 +2,138 @@ use pac::clocks::vals::*;
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use crate::{pac, reset};
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const XOSC_MHZ: u32 = 12;
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static mut EXTERNAL_HZ: u32 = 0;
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pub struct ClockConfig {
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rosc_config: Option<RoscConfig>,
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xosc_config: Option<XoscConfig>,
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ref_clk_config: (RefClkSrc, u8),
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sys_clk_config: (SysClkSrc, u32),
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peri_clk_src: Option<ClkPeriCtrlAuxsrc>,
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usb_clk_config: Option<(ClkUsbCtrlAuxsrc, u8)>,
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adc_clk_config: Option<(ClkAdcCtrlAuxsrc, u8)>,
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rtc_clk_config: Option<(ClkRtcCtrlAuxsrc, u32)>,
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}
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impl ClockConfig {
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pub fn crystal(crystal_hz: u32) -> Self {
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Self {
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rosc_config: Some(RoscConfig {
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range: pac::rosc::vals::FreqRange::MEDIUM,
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drive_strength_0: 0,
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drive_strength_1: 0,
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drive_strength_2: 0,
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drive_strength_3: 0,
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drive_strength_4: 0,
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drive_strength_5: 0,
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drive_strength_6: 0,
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drive_strength_7: 0,
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div: 16,
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}),
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xosc_config: Some(XoscConfig {
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hz: crystal_hz,
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clock_type: ExternalClock::Crystal,
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sys_pll: Some(PllConfig {
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refdiv: 1,
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vco_freq: 1500_000_000,
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post_div1: 6,
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post_div2: 2,
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}),
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usb_pll: Some(PllConfig {
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refdiv: 1,
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vco_freq: 480_000_000,
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post_div1: 5,
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post_div2: 2,
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}),
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}),
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ref_clk_config: (RefClkSrc::Xosc, 1),
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sys_clk_config: (SysClkSrc::Aux(ClkSysCtrlAuxsrc::CLKSRC_PLL_SYS), 1),
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peri_clk_src: Some(ClkPeriCtrlAuxsrc::CLK_SYS),
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usb_clk_config: Some((ClkUsbCtrlAuxsrc::CLKSRC_PLL_SYS, 1)),
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adc_clk_config: Some((ClkAdcCtrlAuxsrc::CLKSRC_PLL_USB, 1)),
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rtc_clk_config: Some((ClkRtcCtrlAuxsrc::CLKSRC_PLL_USB, 1024)),
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}
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}
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pub fn rosc() -> Self {
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Self {
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rosc_config: Some(RoscConfig {
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range: pac::rosc::vals::FreqRange::HIGH,
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drive_strength_0: 0,
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drive_strength_1: 0,
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drive_strength_2: 0,
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drive_strength_3: 0,
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drive_strength_4: 0,
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drive_strength_5: 0,
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drive_strength_6: 0,
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drive_strength_7: 0,
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div: 1,
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}),
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xosc_config: None,
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ref_clk_config: (RefClkSrc::Rosc, 4),
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sys_clk_config: (SysClkSrc::Aux(ClkSysCtrlAuxsrc::ROSC_CLKSRC), 1),
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peri_clk_src: Some(ClkPeriCtrlAuxsrc::ROSC_CLKSRC_PH),
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usb_clk_config: None,
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adc_clk_config: Some((ClkAdcCtrlAuxsrc::ROSC_CLKSRC_PH, 1)),
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rtc_clk_config: Some((ClkRtcCtrlAuxsrc::ROSC_CLKSRC_PH, 1024)),
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}
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}
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}
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pub enum ExternalClock {
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Crystal,
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Clock,
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}
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pub struct XoscConfig {
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hz: u32,
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clock_type: ExternalClock,
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sys_pll: Option<PllConfig>,
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usb_pll: Option<PllConfig>,
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}
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pub struct RoscConfig {
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range: pac::rosc::vals::FreqRange,
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drive_strength_0: u8,
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drive_strength_1: u8,
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drive_strength_2: u8,
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drive_strength_3: u8,
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drive_strength_4: u8,
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drive_strength_5: u8,
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drive_strength_6: u8,
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drive_strength_7: u8,
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div: u16,
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}
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pub struct PllConfig {
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pub refdiv: u32,
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pub vco_freq: u32,
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pub post_div1: u8,
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pub post_div2: u8,
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}
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pub struct RefClkConfig {
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pub src: RefClkSrc,
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pub div: u8,
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}
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pub enum RefClkSrc {
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Xosc,
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Rosc,
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Aux(ClkRefCtrlAuxsrc),
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}
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pub struct SysClkConfig {
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pub src: SysClkSrc,
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pub div: u32,
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}
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pub enum SysClkSrc {
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Ref,
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Aux(ClkSysCtrlAuxsrc),
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}
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/// safety: must be called exactly once at bootup
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pub(crate) unsafe fn init() {
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pub(crate) unsafe fn init(config: ClockConfig) {
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// Reset everything except:
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// - QSPI (we're using it to run this code!)
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// - PLLs (it may be suicide if that's what's clocking us)
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@ -15,124 +143,325 @@ pub(crate) unsafe fn init() {
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peris.set_pads_qspi(false);
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peris.set_pll_sys(false);
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peris.set_pll_usb(false);
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// TODO investigate if usb should be unreset here
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peris.set_usbctrl(false);
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peris.set_syscfg(false);
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reset::reset(peris);
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// Remove reset from peripherals which are clocked only by clk_sys and
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// clk_ref. Other peripherals stay in reset until we've configured clocks.
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let mut peris = reset::ALL_PERIPHERALS;
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peris.set_adc(false);
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peris.set_rtc(false);
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peris.set_spi0(false);
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peris.set_spi1(false);
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peris.set_uart0(false);
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peris.set_uart1(false);
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peris.set_usbctrl(false);
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reset::unreset_wait(peris);
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// Start tick in watchdog
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// xosc 12 mhz
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pac::WATCHDOG.tick().write(|w| {
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w.set_cycles(XOSC_MHZ as u16);
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w.set_enable(true);
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});
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// Disable resus that may be enabled from previous software
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let c = pac::CLOCKS;
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c.clk_sys_resus_ctrl()
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.write_value(pac::clocks::regs::ClkSysResusCtrl(0));
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// start XOSC
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start_xosc();
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// Before we touch PLLs, switch sys and ref cleanly away from their aux sources.
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c.clk_sys_ctrl().modify(|w| w.set_src(ClkSysCtrlSrc::CLK_REF));
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while c.clk_sys_selected().read() != 1 {}
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c.clk_ref_ctrl().modify(|w| w.set_src(ClkRefCtrlSrc::ROSC_CLKSRC_PH));
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while c.clk_ref_selected().read() != 1 {}
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// Configure PLLs
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// REF FBDIV VCO POSTDIV
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// PLL SYS: 12 / 1 = 12MHz * 125 = 1500MHZ / 6 / 2 = 125MHz
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// PLL USB: 12 / 1 = 12MHz * 40 = 480 MHz / 5 / 2 = 48MHz
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configure_pll(pac::PLL_SYS, 1, 1500_000_000, 6, 2);
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configure_pll(pac::PLL_USB, 1, 480_000_000, 5, 2);
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if let Some(config) = config.rosc_config {
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configure_rosc(config);
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}
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// CLK_REF = XOSC (12MHz) / 1 = 12MHz2Mhz
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if let Some(config) = config.xosc_config {
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EXTERNAL_HZ = config.hz;
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pac::WATCHDOG.tick().write(|w| {
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w.set_cycles((config.hz / 1_000_000) as u16);
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w.set_enable(true);
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});
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// start XOSC
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match config.clock_type {
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ExternalClock::Crystal => start_xosc(config.hz),
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// TODO The datasheet says the xosc needs to be put into a bypass mode to use an
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// external clock, but is mum about how to do that.
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ExternalClock::Clock => todo!(),
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}
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if let Some(sys_pll_config) = config.sys_pll {
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configure_pll(pac::PLL_SYS, config.hz, sys_pll_config);
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}
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if let Some(usb_pll_config) = config.usb_pll {
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configure_pll(pac::PLL_USB, config.hz, usb_pll_config);
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}
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}
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let (src, div) = config.ref_clk_config;
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match src {
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RefClkSrc::Xosc => {
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c.clk_ref_ctrl().write(|w| {
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w.set_src(ClkRefCtrlSrc::XOSC_CLKSRC);
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});
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while c.clk_ref_selected().read() != 1 << ClkRefCtrlSrc::XOSC_CLKSRC.0 {}
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c.clk_ref_div().write(|w| w.set_int(1));
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c.clk_ref_div().write(|w| w.set_int(div));
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}
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RefClkSrc::Rosc => {
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c.clk_ref_ctrl().write(|w| {
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w.set_src(ClkRefCtrlSrc::ROSC_CLKSRC_PH);
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});
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while c.clk_ref_selected().read() != 1 << ClkRefCtrlSrc::ROSC_CLKSRC_PH.0 {}
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c.clk_ref_div().write(|w| w.set_int(div));
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}
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RefClkSrc::Aux(src) => {
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c.clk_ref_ctrl().write(|w| {
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w.set_auxsrc(src);
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w.set_src(ClkRefCtrlSrc::CLKSRC_CLK_REF_AUX);
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});
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while c.clk_ref_selected().read() != 1 << ClkRefCtrlSrc::CLKSRC_CLK_REF_AUX.0 {}
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c.clk_ref_div().write(|w| w.set_int(div));
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}
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}
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// CLK SYS = PLL SYS (125MHz) / 1 = 125MHz
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pac::WATCHDOG.tick().write(|w| {
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w.set_cycles((clk_ref_freq() / 1_000_000) as u16);
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w.set_enable(true);
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});
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let (src, div) = config.sys_clk_config;
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match src {
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SysClkSrc::Ref => {
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c.clk_sys_ctrl().write(|w| {
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w.set_src(ClkSysCtrlSrc::CLK_REF);
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});
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while c.clk_sys_selected().read() != 1 << ClkSysCtrlSrc::CLK_REF.0 {}
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c.clk_sys_div().write(|w| w.set_int(1));
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c.clk_sys_div().write(|w| w.set_int(div));
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}
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SysClkSrc::Aux(src) => {
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c.clk_sys_ctrl().write(|w| {
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w.set_auxsrc(ClkSysCtrlAuxsrc::CLKSRC_PLL_SYS);
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w.set_src(ClkSysCtrlSrc::CLK_REF);
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});
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while c.clk_sys_selected().read() != 1 << ClkSysCtrlSrc::CLK_REF.0 {}
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c.clk_sys_div().write(|w| w.set_int(div));
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c.clk_sys_ctrl().write(|w| {
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w.set_auxsrc(src);
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w.set_src(ClkSysCtrlSrc::CLKSRC_CLK_SYS_AUX);
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});
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while c.clk_sys_selected().read() != 1 << ClkSysCtrlSrc::CLKSRC_CLK_SYS_AUX.0 {}
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}
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}
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let mut peris = reset::ALL_PERIPHERALS;
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if let Some(src) = config.peri_clk_src {
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c.clk_peri_ctrl().write(|w| {
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w.set_enable(true);
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w.set_auxsrc(src);
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});
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} else {
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peris.set_spi0(false);
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peris.set_spi1(false);
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peris.set_uart0(false);
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peris.set_uart1(false);
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}
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if let Some((src, div)) = config.usb_clk_config {
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// CLK USB = PLL USB (48MHz) / 1 = 48MHz
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c.clk_usb_div().write(|w| w.set_int(1));
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c.clk_usb_div().write(|w| w.set_int(div));
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c.clk_usb_ctrl().write(|w| {
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w.set_enable(true);
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w.set_auxsrc(ClkUsbCtrlAuxsrc::CLKSRC_PLL_USB);
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w.set_auxsrc(src);
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});
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} else {
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peris.set_usbctrl(false);
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}
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if let Some((src, div)) = config.adc_clk_config {
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// CLK ADC = PLL USB (48MHZ) / 1 = 48MHz
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c.clk_adc_div().write(|w| w.set_int(1));
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c.clk_adc_div().write(|w| w.set_int(div));
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c.clk_adc_ctrl().write(|w| {
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w.set_enable(true);
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w.set_auxsrc(ClkAdcCtrlAuxsrc::CLKSRC_PLL_USB);
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w.set_auxsrc(src);
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});
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} else {
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peris.set_adc(false);
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}
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if let Some((src, div)) = config.rtc_clk_config {
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// CLK RTC = PLL USB (48MHz) / 1024 = 46875Hz
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c.clk_rtc_ctrl().modify(|w| {
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w.set_enable(false);
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});
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c.clk_rtc_div().write(|w| w.set_int(1024));
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c.clk_rtc_div().write(|w| w.set_int(div));
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c.clk_rtc_ctrl().write(|w| {
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w.set_enable(true);
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w.set_auxsrc(ClkRtcCtrlAuxsrc::CLKSRC_PLL_USB);
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});
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// CLK PERI = clk_sys. Used as reference clock for Peripherals. No dividers so just select and enable
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// Normally choose clk_sys or clk_usb
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c.clk_peri_ctrl().write(|w| {
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w.set_enable(true);
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w.set_auxsrc(ClkPeriCtrlAuxsrc::CLK_SYS);
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w.set_auxsrc(src);
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});
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} else {
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peris.set_rtc(false);
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}
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// Peripheral clocks should now all be running
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let peris = reset::ALL_PERIPHERALS;
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reset::unreset_wait(peris);
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}
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pub(crate) fn _clk_sys_freq() -> u32 {
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125_000_000
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unsafe fn configure_rosc(config: RoscConfig) {
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let p = pac::ROSC;
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p.freqa().write(|w| {
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w.set_passwd(pac::rosc::vals::Passwd::PASS);
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w.set_ds0(config.drive_strength_0);
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w.set_ds1(config.drive_strength_1);
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w.set_ds2(config.drive_strength_2);
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w.set_ds3(config.drive_strength_3);
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});
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p.freqb().write(|w| {
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w.set_passwd(pac::rosc::vals::Passwd::PASS);
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w.set_ds4(config.drive_strength_4);
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w.set_ds5(config.drive_strength_5);
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w.set_ds6(config.drive_strength_6);
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w.set_ds7(config.drive_strength_7);
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});
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p.div().write(|w| {
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w.set_div(pac::rosc::vals::Div(config.div + pac::rosc::vals::Div::PASS.0));
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});
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p.ctrl().write(|w| {
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w.set_enable(pac::rosc::vals::Enable::ENABLE);
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w.set_freq_range(config.range);
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});
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}
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pub fn estimate_rosc_freq() -> u32 {
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let p = pac::ROSC;
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let base = match unsafe { p.ctrl().read().freq_range() } {
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pac::rosc::vals::FreqRange::LOW => 84_000_000,
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pac::rosc::vals::FreqRange::MEDIUM => 104_000_000,
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pac::rosc::vals::FreqRange::HIGH => 140_000_000,
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pac::rosc::vals::FreqRange::TOOHIGH => 208_000_000,
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_ => unreachable!(),
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};
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let mut div = unsafe { p.div().read().0 - pac::rosc::vals::Div::PASS.0 as u32 };
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if div == 0 {
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div = 32
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}
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base / div
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}
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pub(crate) fn clk_sys_freq() -> u32 {
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let c = pac::CLOCKS;
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let ctrl = unsafe { c.clk_sys_ctrl().read() };
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let base = match ctrl.src() {
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ClkSysCtrlSrc::CLK_REF => clk_ref_freq(),
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ClkSysCtrlSrc::CLKSRC_CLK_SYS_AUX => {
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match ctrl.auxsrc() {
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ClkSysCtrlAuxsrc::CLKSRC_PLL_SYS => clk_sys_pll_freq(),
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ClkSysCtrlAuxsrc::CLKSRC_PLL_USB => clk_usb_pll_freq(),
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ClkSysCtrlAuxsrc::ROSC_CLKSRC => estimate_rosc_freq(),
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ClkSysCtrlAuxsrc::XOSC_CLKSRC => unsafe { EXTERNAL_HZ },
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// TODO not sure how to handle clkin sources
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_ => todo!(),
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}
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}
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_ => unreachable!(),
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};
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let div = unsafe { c.clk_sys_div().read() };
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let int = if div.int() == 0 { 65536 } else { div.int() };
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// TODO handle fractional clock div
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let _frac = div.frac();
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base / int
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}
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pub(crate) fn clk_sys_pll_freq() -> u32 {
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let p = pac::PLL_SYS;
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let input_freq = unsafe { EXTERNAL_HZ };
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let cs = unsafe { p.cs().read() };
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let refdiv = cs.refdiv() as u32;
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let fbdiv = unsafe { p.fbdiv_int().read().fbdiv_int() } as u32;
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let (postdiv1, postdiv2) = unsafe {
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let prim = p.prim().read();
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(prim.postdiv1() as u32, prim.postdiv2() as u32)
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};
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(((input_freq / refdiv) * fbdiv) / postdiv1) / postdiv2
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}
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pub(crate) fn clk_usb_pll_freq() -> u32 {
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let p = pac::PLL_USB;
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let input_freq = unsafe { EXTERNAL_HZ };
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||||
let cs = unsafe { p.cs().read() };
|
||||
|
||||
let refdiv = cs.refdiv() as u32;
|
||||
let fbdiv = unsafe { p.fbdiv_int().read().fbdiv_int() } as u32;
|
||||
let (postdiv1, postdiv2) = unsafe {
|
||||
let prim = p.prim().read();
|
||||
(prim.postdiv1() as u32, prim.postdiv2() as u32)
|
||||
};
|
||||
|
||||
(((input_freq / refdiv) * fbdiv) / postdiv1) / postdiv2
|
||||
}
|
||||
|
||||
pub(crate) fn clk_peri_freq() -> u32 {
|
||||
125_000_000
|
||||
let c = pac::CLOCKS;
|
||||
let src = unsafe { c.clk_peri_ctrl().read().auxsrc() };
|
||||
|
||||
match src {
|
||||
ClkPeriCtrlAuxsrc::CLK_SYS => clk_sys_freq(),
|
||||
ClkPeriCtrlAuxsrc::CLKSRC_PLL_SYS => clk_sys_pll_freq(),
|
||||
ClkPeriCtrlAuxsrc::ROSC_CLKSRC_PH => estimate_rosc_freq(),
|
||||
ClkPeriCtrlAuxsrc::XOSC_CLKSRC => unsafe { EXTERNAL_HZ },
|
||||
// TODO not sure how to handle clkin sources
|
||||
_ => todo!(),
|
||||
}
|
||||
}
|
||||
|
||||
pub fn clk_ref_freq() -> u32 {
|
||||
let c = pac::CLOCKS;
|
||||
let ctrl = unsafe { c.clk_ref_ctrl().read() };
|
||||
|
||||
let base = match ctrl.src() {
|
||||
ClkRefCtrlSrc::ROSC_CLKSRC_PH => estimate_rosc_freq(),
|
||||
ClkRefCtrlSrc::XOSC_CLKSRC => unsafe { EXTERNAL_HZ },
|
||||
ClkRefCtrlSrc::CLKSRC_CLK_REF_AUX => todo!(),
|
||||
_ => unreachable!(),
|
||||
};
|
||||
|
||||
let mut div = unsafe { c.clk_ref_div().read().int() } as u32;
|
||||
if div == 0 {
|
||||
div = 4;
|
||||
}
|
||||
|
||||
base / div
|
||||
}
|
||||
|
||||
pub(crate) fn clk_rtc_freq() -> u32 {
|
||||
46875
|
||||
let c = pac::CLOCKS;
|
||||
let src = unsafe { c.clk_rtc_ctrl().read().auxsrc() };
|
||||
|
||||
let base = match src {
|
||||
ClkRtcCtrlAuxsrc::XOSC_CLKSRC => unsafe { EXTERNAL_HZ },
|
||||
ClkRtcCtrlAuxsrc::ROSC_CLKSRC_PH => estimate_rosc_freq(),
|
||||
ClkRtcCtrlAuxsrc::CLKSRC_PLL_USB => clk_usb_pll_freq(),
|
||||
ClkRtcCtrlAuxsrc::CLKSRC_PLL_SYS => clk_sys_pll_freq(),
|
||||
// TODO not sure how to handle clkin sources
|
||||
_ => todo!(),
|
||||
};
|
||||
|
||||
let div = unsafe { c.clk_rtc_div().read() };
|
||||
let int = if div.int() == 0 { 65536 } else { div.int() };
|
||||
// TODO handle fractional clock div
|
||||
let _frac = div.frac();
|
||||
|
||||
base / int
|
||||
}
|
||||
|
||||
unsafe fn start_xosc() {
|
||||
const XOSC_MHZ: u32 = 12;
|
||||
unsafe fn start_xosc(crystal_hz: u32) {
|
||||
pac::XOSC
|
||||
.ctrl()
|
||||
.write(|w| w.set_freq_range(pac::xosc::vals::CtrlFreqRange::_1_15MHZ));
|
||||
|
||||
let startup_delay = (((XOSC_MHZ * 1_000_000) / 1000) + 128) / 256;
|
||||
let startup_delay = ((crystal_hz / 1000) + 128) / 256;
|
||||
pac::XOSC.startup().write(|w| w.set_delay(startup_delay as u16));
|
||||
pac::XOSC.ctrl().write(|w| {
|
||||
w.set_freq_range(pac::xosc::vals::CtrlFreqRange::_1_15MHZ);
|
||||
@ -141,24 +470,24 @@ unsafe fn start_xosc() {
|
||||
while !pac::XOSC.status().read().stable() {}
|
||||
}
|
||||
|
||||
unsafe fn configure_pll(p: pac::pll::Pll, refdiv: u32, vco_freq: u32, post_div1: u8, post_div2: u8) {
|
||||
let ref_freq = XOSC_MHZ * 1_000_000 / refdiv;
|
||||
unsafe fn configure_pll(p: pac::pll::Pll, input_freq: u32, config: PllConfig) {
|
||||
let ref_freq = input_freq / config.refdiv;
|
||||
|
||||
let fbdiv = vco_freq / ref_freq;
|
||||
let fbdiv = config.vco_freq / ref_freq;
|
||||
assert!(fbdiv >= 16 && fbdiv <= 320);
|
||||
assert!(post_div1 >= 1 && post_div1 <= 7);
|
||||
assert!(post_div2 >= 1 && post_div2 <= 7);
|
||||
assert!(post_div2 <= post_div1);
|
||||
assert!(ref_freq <= (vco_freq / 16));
|
||||
assert!(config.post_div1 >= 1 && config.post_div1 <= 7);
|
||||
assert!(config.post_div2 >= 1 && config.post_div2 <= 7);
|
||||
assert!(config.post_div2 <= config.post_div1);
|
||||
assert!(ref_freq <= (config.vco_freq / 16));
|
||||
|
||||
// do not disrupt PLL that is already correctly configured and operating
|
||||
let cs = p.cs().read();
|
||||
let prim = p.prim().read();
|
||||
if cs.lock()
|
||||
&& cs.refdiv() == refdiv as u8
|
||||
&& cs.refdiv() == config.refdiv as u8
|
||||
&& p.fbdiv_int().read().fbdiv_int() == fbdiv as u16
|
||||
&& prim.postdiv1() == post_div1
|
||||
&& prim.postdiv2() == post_div2
|
||||
&& prim.postdiv1() == config.post_div1
|
||||
&& prim.postdiv2() == config.post_div2
|
||||
{
|
||||
return;
|
||||
}
|
||||
@ -174,7 +503,7 @@ unsafe fn configure_pll(p: pac::pll::Pll, refdiv: u32, vco_freq: u32, post_div1:
|
||||
reset::unreset_wait(peris);
|
||||
|
||||
// Load VCO-related dividers before starting VCO
|
||||
p.cs().write(|w| w.set_refdiv(refdiv as _));
|
||||
p.cs().write(|w| w.set_refdiv(config.refdiv as _));
|
||||
p.fbdiv_int().write(|w| w.set_fbdiv_int(fbdiv as _));
|
||||
|
||||
// Turn on PLL
|
||||
@ -189,8 +518,8 @@ unsafe fn configure_pll(p: pac::pll::Pll, refdiv: u32, vco_freq: u32, post_div1:
|
||||
|
||||
// Wait for PLL to lock
|
||||
p.prim().write(|w| {
|
||||
w.set_postdiv1(post_div1);
|
||||
w.set_postdiv2(post_div2);
|
||||
w.set_postdiv1(config.post_div1);
|
||||
w.set_postdiv2(config.post_div2);
|
||||
});
|
||||
|
||||
// Turn on post divider
|
||||
|
||||
@ -136,23 +136,35 @@ embassy_hal_common::peripherals! {
|
||||
static BOOT2: [u8; 256] = *include_bytes!("boot2.bin");
|
||||
|
||||
pub mod config {
|
||||
use crate::clocks::ClockConfig;
|
||||
|
||||
#[non_exhaustive]
|
||||
pub struct Config {}
|
||||
pub struct Config {
|
||||
pub clocks: ClockConfig,
|
||||
}
|
||||
|
||||
impl Default for Config {
|
||||
fn default() -> Self {
|
||||
Self {}
|
||||
Self {
|
||||
clocks: ClockConfig::crystal(12_000_000),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Config {
|
||||
pub fn new(clocks: ClockConfig) -> Self {
|
||||
Self { clocks }
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub fn init(_config: config::Config) -> Peripherals {
|
||||
pub fn init(config: config::Config) -> Peripherals {
|
||||
// Do this first, so that it panics if user is calling `init` a second time
|
||||
// before doing anything important.
|
||||
let peripherals = Peripherals::take();
|
||||
|
||||
unsafe {
|
||||
clocks::init();
|
||||
clocks::init(config.clocks);
|
||||
#[cfg(feature = "time-driver")]
|
||||
timer::init();
|
||||
dma::init();
|
||||
|
||||
Loading…
Reference in New Issue
Block a user