diff --git a/embassy-executor/CHANGELOG.md b/embassy-executor/CHANGELOG.md
index cade48f0..e7914cbc 100644
--- a/embassy-executor/CHANGELOG.md
+++ b/embassy-executor/CHANGELOG.md
@@ -5,6 +5,11 @@ All notable changes to this project will be documented in this file.
The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
+## 0.3.2 - 2023-11-06
+
+- Use `atomic-polyfill` for `riscv32`
+- Removed unused dependencies (static_cell, futures-util)
+
## 0.3.1 - 2023-11-01
- Fix spurious "Found waker not created by the Embassy executor" error in recent nightlies.
diff --git a/embassy-executor/Cargo.toml b/embassy-executor/Cargo.toml
index 8e36637a..a85c5dff 100644
--- a/embassy-executor/Cargo.toml
+++ b/embassy-executor/Cargo.toml
@@ -1,6 +1,6 @@
[package]
name = "embassy-executor"
-version = "0.3.1"
+version = "0.3.2"
edition = "2021"
license = "MIT OR Apache-2.0"
description = "async/await executor designed for embedded usage"
@@ -57,7 +57,6 @@ defmt = { version = "0.3", optional = true }
log = { version = "0.4.14", optional = true }
rtos-trace = { version = "0.1.2", optional = true }
-futures-util = { version = "0.3.17", default-features = false }
embassy-macros = { version = "0.2.1", path = "../embassy-macros" }
embassy-time = { version = "0.1.5", path = "../embassy-time", optional = true}
atomic-polyfill = "1.0.1"
diff --git a/embassy-executor/src/arch/riscv32.rs b/embassy-executor/src/arch/riscv32.rs
index 40c6877e..e5c0ff2e 100644
--- a/embassy-executor/src/arch/riscv32.rs
+++ b/embassy-executor/src/arch/riscv32.rs
@@ -6,8 +6,8 @@ pub use thread::*;
#[cfg(feature = "executor-thread")]
mod thread {
use core::marker::PhantomData;
- use core::sync::atomic::{AtomicBool, Ordering};
+ use atomic_polyfill::{AtomicBool, Ordering};
#[cfg(feature = "nightly")]
pub use embassy_macros::main_riscv as main;
diff --git a/embassy-net-esp-hosted/Cargo.toml b/embassy-net-esp-hosted/Cargo.toml
index eba54249..2a8c2857 100644
--- a/embassy-net-esp-hosted/Cargo.toml
+++ b/embassy-net-esp-hosted/Cargo.toml
@@ -15,7 +15,7 @@ embassy-net-driver-channel = { version = "0.2.0", path = "../embassy-net-driver-
embedded-hal = { version = "1.0.0-rc.1" }
embedded-hal-async = { version = "=1.0.0-rc.1" }
-noproto = { git="https://github.com/embassy-rs/noproto", default-features = false, features = ["derive"] }
+noproto = { git="https://github.com/embassy-rs/noproto", rev = "c90f3a78d7b5642415e0a07af401320b84d8ab6f", default-features = false, features = ["derive"] }
#noproto = { version = "0.1", path = "/home/dirbaio/noproto", default-features = false, features = ["derive"] }
heapless = "0.7.16"
diff --git a/embassy-net/CHANGELOG.md b/embassy-net/CHANGELOG.md
index 4030e050..ada34cb7 100644
--- a/embassy-net/CHANGELOG.md
+++ b/embassy-net/CHANGELOG.md
@@ -5,6 +5,10 @@ All notable changes to this project will be documented in this file.
The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
+## Unreleased
+
+- Avoid never resolving `TcpIo::read` when the output buffer is empty.
+
## 0.2.1 - 2023-10-31
- Re-add impl_trait_projections
diff --git a/embassy-net/README.md b/embassy-net/README.md
index 7bb2283c..52d048e6 100644
--- a/embassy-net/README.md
+++ b/embassy-net/README.md
@@ -4,7 +4,7 @@
It builds on [`smoltcp`](https://github.com/smoltcp-rs/smoltcp). It provides a higher-level and more opinionated
API. It glues together the components provided by `smoltcp`, handling the low-level details with defaults and
-memory management designed to work well for embedded systems, aiiming for a more "Just Works" experience.
+memory management designed to work well for embedded systems, aiming for a more "Just Works" experience.
## Features
diff --git a/embassy-net/src/tcp.rs b/embassy-net/src/tcp.rs
index b5615cb6..bcd5bb61 100644
--- a/embassy-net/src/tcp.rs
+++ b/embassy-net/src/tcp.rs
@@ -390,6 +390,13 @@ impl<'d> TcpIo<'d> {
// CAUTION: smoltcp semantics around EOF are different to what you'd expect
// from posix-like IO, so we have to tweak things here.
self.with_mut(|s, _| match s.recv_slice(buf) {
+ // Reading into empty buffer
+ Ok(0) if buf.is_empty() => {
+ // embedded_io_async::Read's contract is to not block if buf is empty. While
+ // this function is not a direct implementor of the trait method, we still don't
+ // want our future to never resolve.
+ Poll::Ready(Ok(0))
+ }
// No data ready
Ok(0) => {
s.register_recv_waker(cx.waker());
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 2a2df5c5..7b3a6c2b 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -18,7 +18,7 @@ flavors = [
{ regex_feature = "stm32f7.*", target = "thumbv7em-none-eabi" },
{ regex_feature = "stm32c0.*", target = "thumbv6m-none-eabi" },
{ regex_feature = "stm32g0.*", target = "thumbv6m-none-eabi" },
- { regex_feature = "stm32g4.*", target = "thumbv7em-none-eabi" },
+ { regex_feature = "stm32g4.*", target = "thumbv7em-none-eabi", features = ["low-power"] },
{ regex_feature = "stm32h5.*", target = "thumbv8m.main-none-eabihf" },
{ regex_feature = "stm32h7.*", target = "thumbv7em-none-eabi" },
{ regex_feature = "stm32l0.*", target = "thumbv6m-none-eabi", features = ["low-power"] },
@@ -58,7 +58,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
critical-section = "1.1"
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-73b8c37ae74fc28b247188c989fd99400611bd6b" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-1374ed622714ef4702826699ca21cc1f741f4133" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -76,7 +76,7 @@ critical-section = { version = "1.1", features = ["std"] }
[build-dependencies]
proc-macro2 = "1.0.36"
quote = "1.0.15"
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-73b8c37ae74fc28b247188c989fd99400611bd6b", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-1374ed622714ef4702826699ca21cc1f741f4133", default-features = false, features = ["metadata"]}
[features]
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 276c1d63..6b41cd39 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -6,7 +6,7 @@ use std::{env, fs};
use proc_macro2::{Ident, TokenStream};
use quote::{format_ident, quote};
use stm32_metapac::metadata::ir::{BlockItemInner, Enum, FieldSet};
-use stm32_metapac::metadata::{MemoryRegionKind, PeripheralRccRegister, METADATA};
+use stm32_metapac::metadata::{MemoryRegionKind, PeripheralRccRegister, StopMode, METADATA};
fn main() {
let target = env::var("TARGET").unwrap();
@@ -557,18 +557,18 @@ fn main() {
};
/*
- If LP and non-LP peripherals share the same RCC enable bit, then a refcount leak will result.
+ A refcount leak can result if the same field is shared by peripherals with different stop modes
- This should be checked in stm32-data-gen.
+ This condition should be checked in stm32-data
*/
- let stop_refcount = if p.name.starts_with("LP") {
- quote! { REFCOUNT_STOP2 }
- } else {
- quote! { REFCOUNT_STOP1 }
+ let stop_refcount = match rcc.stop_mode {
+ StopMode::Standby => None,
+ StopMode::Stop2 => Some(quote! { REFCOUNT_STOP2 }),
+ StopMode::Stop1 => Some(quote! { REFCOUNT_STOP1 }),
};
- let (incr_stop_refcount, decr_stop_refcount) = if p.name != "RTC" {
- (
+ let (incr_stop_refcount, decr_stop_refcount) = match stop_refcount {
+ Some(stop_refcount) => (
quote! {
#[cfg(feature = "low-power")]
unsafe { crate::rcc::#stop_refcount += 1 };
@@ -577,9 +577,8 @@ fn main() {
#[cfg(feature = "low-power")]
unsafe { crate::rcc::#stop_refcount -= 1 };
},
- )
- } else {
- (quote! {}, quote! {})
+ ),
+ None => (TokenStream::new(), TokenStream::new()),
};
g.extend(quote! {
@@ -828,7 +827,7 @@ fn main() {
(("fmc", "NCE"), quote!(crate::fmc::NCEPin)),
(("fmc", "NOE"), quote!(crate::fmc::NOEPin)),
(("fmc", "NWE"), quote!(crate::fmc::NWEPin)),
- (("fmc", "Clk"), quote!(crate::fmc::ClkPin)),
+ (("fmc", "CLK"), quote!(crate::fmc::ClkPin)),
(("fmc", "BA0"), quote!(crate::fmc::BA0Pin)),
(("fmc", "BA1"), quote!(crate::fmc::BA1Pin)),
(("timer", "CH1"), quote!(crate::timer::Channel1Pin)),
@@ -944,17 +943,23 @@ fn main() {
}
if regs.kind == "opamp" {
- if !pin.signal.starts_with("VP") {
- continue;
+ if pin.signal.starts_with("VP") {
+ // Impl NonInvertingPin for the VP* signals (VP0, VP1, VP2, etc)
+ let peri = format_ident!("{}", p.name);
+ let pin_name = format_ident!("{}", pin.pin);
+ let ch: u8 = pin.signal.strip_prefix("VP").unwrap().parse().unwrap();
+
+ g.extend(quote! {
+ impl_opamp_vp_pin!( #peri, #pin_name, #ch);
+ })
+ } else if pin.signal == "VOUT" {
+ // Impl OutputPin for the VOUT pin
+ let peri = format_ident!("{}", p.name);
+ let pin_name = format_ident!("{}", pin.pin);
+ g.extend(quote! {
+ impl_opamp_vout_pin!( #peri, #pin_name );
+ })
}
-
- let peri = format_ident!("{}", p.name);
- let pin_name = format_ident!("{}", pin.pin);
- let ch: u8 = pin.signal.strip_prefix("VP").unwrap().parse().unwrap();
-
- g.extend(quote! {
- impl_opamp_pin!( #peri, #pin_name, #ch);
- })
}
// DAC is special
diff --git a/embassy-stm32/src/eth/v2/descriptors.rs b/embassy-stm32/src/eth/v2/descriptors.rs
index e9799adf..01ea8e57 100644
--- a/embassy-stm32/src/eth/v2/descriptors.rs
+++ b/embassy-stm32/src/eth/v2/descriptors.rs
@@ -119,13 +119,11 @@ impl<'a> TDesRing<'a> {
// "Preceding reads and writes cannot be moved past subsequent writes."
fence(Ordering::Release);
- self.index = self.index + 1;
- if self.index == self.descriptors.len() {
- self.index = 0;
- }
-
// signal DMA it can try again.
- ETH.ethernet_dma().dmactx_dtpr().write(|w| w.0 = 0)
+ // See issue #2129
+ ETH.ethernet_dma().dmactx_dtpr().write(|w| w.0 = &td as *const _ as u32);
+
+ self.index = (self.index + 1) % self.descriptors.len();
}
}
@@ -237,21 +235,19 @@ impl<'a> RDesRing<'a> {
/// Pop the packet previously returned by `available`.
pub(crate) fn pop_packet(&mut self) {
- let descriptor = &mut self.descriptors[self.index];
- assert!(descriptor.available());
+ let rd = &mut self.descriptors[self.index];
+ assert!(rd.available());
- self.descriptors[self.index].set_ready(self.buffers[self.index].0.as_mut_ptr());
+ rd.set_ready(self.buffers[self.index].0.as_mut_ptr());
// "Preceding reads and writes cannot be moved past subsequent writes."
fence(Ordering::Release);
// signal DMA it can try again.
- ETH.ethernet_dma().dmacrx_dtpr().write(|w| w.0 = 0);
+ // See issue #2129
+ ETH.ethernet_dma().dmacrx_dtpr().write(|w| w.0 = &rd as *const _ as u32);
// Increment index.
- self.index += 1;
- if self.index == self.descriptors.len() {
- self.index = 0
- }
+ self.index = (self.index + 1) % self.descriptors.len();
}
}
diff --git a/embassy-stm32/src/fmc.rs b/embassy-stm32/src/fmc.rs
index d6e25996..dd0d2721 100644
--- a/embassy-stm32/src/fmc.rs
+++ b/embassy-stm32/src/fmc.rs
@@ -12,6 +12,37 @@ pub struct Fmc<'d, T: Instance> {
unsafe impl<'d, T> Send for Fmc<'d, T> where T: Instance {}
+impl<'d, T> Fmc<'d, T>
+where
+ T: Instance,
+{
+ /// Create a raw FMC instance.
+ ///
+ /// **Note:** This is currently used to provide access to some basic FMC functions
+ /// for manual configuration for memory types that stm32-fmc does not support.
+ pub fn new_raw(_instance: impl Peripheral
+ 'd) -> Self {
+ Self { peri: PhantomData }
+ }
+
+ /// Enable the FMC peripheral and reset it.
+ pub fn enable(&mut self) {
+ T::enable_and_reset();
+ }
+
+ /// Enable the memory controller on applicable chips.
+ pub fn memory_controller_enable(&mut self) {
+ // fmc v1 and v2 does not have the fmcen bit
+ // fsmc v1, v2 and v3 does not have the fmcen bit
+ // This is a "not" because it is expected that all future versions have this bit
+ #[cfg(not(any(fmc_v1x3, fmc_v2x1, fsmc_v1x0, fsmc_v1x3, fsmc_v2x3, fsmc_v3x1)))]
+ T::REGS.bcr1().modify(|r| r.set_fmcen(true));
+ }
+
+ pub fn source_clock_hz(&self) -> u32 {
+ ::frequency().0
+ }
+}
+
unsafe impl<'d, T> stm32_fmc::FmcPeripheral for Fmc<'d, T>
where
T: Instance,
diff --git a/embassy-stm32/src/opamp.rs b/embassy-stm32/src/opamp.rs
index cb55cbe1..89db6d14 100644
--- a/embassy-stm32/src/opamp.rs
+++ b/embassy-stm32/src/opamp.rs
@@ -13,21 +13,50 @@ pub enum OpAmpGain {
Mul16,
}
-pub struct OpAmpOutput<'d, 'p, T: Instance, P: NonInvertingPin> {
- _inner: &'d OpAmp<'d, T>,
- _input: &'p mut P,
+#[derive(Clone, Copy)]
+pub enum OpAmpSpeed {
+ Normal,
+ HighSpeed,
}
+#[cfg(opamp_g4)]
+impl From for crate::pac::opamp::vals::OpampCsrOpahsm {
+ fn from(v: OpAmpSpeed) -> Self {
+ match v {
+ OpAmpSpeed::Normal => crate::pac::opamp::vals::OpampCsrOpahsm::NORMAL,
+ OpAmpSpeed::HighSpeed => crate::pac::opamp::vals::OpampCsrOpahsm::HIGHSPEED,
+ }
+ }
+}
+
+/// OpAmp external outputs, wired to a GPIO pad.
+///
+/// The GPIO output pad is held by this struct to ensure it cannot be used elsewhere.
+///
+/// This struct can also be used as an ADC input.
+pub struct OpAmpOutput<'d, 'p, T: Instance, P: OutputPin> {
+ _inner: &'d OpAmp<'d, T>,
+ _output: &'p mut P,
+}
+
+/// OpAmp internal outputs, wired directly to ADC inputs.
+///
+/// This struct can be used as an ADC input.
+pub struct OpAmpInternalOutput<'d, T: Instance> {
+ _inner: &'d OpAmp<'d, T>,
+}
+
+/// OpAmp driver.
pub struct OpAmp<'d, T: Instance> {
_inner: PeripheralRef<'d, T>,
}
impl<'d, T: Instance> OpAmp<'d, T> {
- pub fn new(opamp: impl Peripheral + 'd) -> Self {
- Self::new_inner(opamp)
- }
-
- fn new_inner(opamp: impl Peripheral
+ 'd) -> Self {
+ /// Create a new driver instance.
+ ///
+ /// Enables the OpAmp and configures the speed, but
+ /// does not set any other configuration.
+ pub fn new(opamp: impl Peripheral
+ 'd, #[cfg(opamp_g4)] speed: OpAmpSpeed) -> Self {
into_ref!(opamp);
#[cfg(opamp_f3)]
@@ -38,15 +67,34 @@ impl<'d, T: Instance> OpAmp<'d, T> {
#[cfg(opamp_g4)]
T::regs().opamp_csr().modify(|w| {
w.set_opaen(true);
+ w.set_opahsm(speed.into());
});
Self { _inner: opamp }
}
- pub fn buffer_for<'a, 'b, P>(&'a mut self, pin: &'b mut P, gain: OpAmpGain) -> OpAmpOutput<'a, 'b, T, P>
+ /// Configure the OpAmp as a buffer for the provided input pin,
+ /// outputting to the provided output pin.
+ ///
+ /// The input pin is configured for analogue mode but not consumed,
+ /// so it may subsequently be used for ADC or comparator inputs.
+ ///
+ /// The output pin is held within the returned [`OpAmpOutput`] struct,
+ /// preventing it being used elsewhere. The `OpAmpOutput` can then be
+ /// directly used as an ADC input.
+ pub fn buffer_ext<'a, 'b, IP, OP>(
+ &'a mut self,
+ in_pin: &IP,
+ out_pin: &'b mut OP,
+ gain: OpAmpGain,
+ ) -> OpAmpOutput<'a, 'b, T, OP>
where
- P: NonInvertingPin,
+ IP: NonInvertingPin + crate::gpio::sealed::Pin,
+ OP: OutputPin + crate::gpio::sealed::Pin,
{
+ in_pin.set_as_analog();
+ out_pin.set_as_analog();
+
let (vm_sel, pga_gain) = match gain {
OpAmpGain::Mul1 => (0b11, 0b00),
OpAmpGain::Mul2 => (0b10, 0b00),
@@ -57,25 +105,76 @@ impl<'d, T: Instance> OpAmp<'d, T> {
#[cfg(opamp_f3)]
T::regs().opampcsr().modify(|w| {
- w.set_vp_sel(pin.channel());
+ w.set_vp_sel(in_pin.channel());
w.set_vm_sel(vm_sel);
w.set_pga_gain(pga_gain);
+ w.set_opampen(true);
});
#[cfg(opamp_g4)]
T::regs().opamp_csr().modify(|w| {
use crate::pac::opamp::vals::*;
- w.set_vp_sel(OpampCsrVpSel::from_bits(pin.channel()));
+ w.set_vp_sel(OpampCsrVpSel::from_bits(in_pin.channel()));
w.set_vm_sel(OpampCsrVmSel::from_bits(vm_sel));
w.set_pga_gain(OpampCsrPgaGain::from_bits(pga_gain));
+ w.set_opaintoen(OpampCsrOpaintoen::OUTPUTPIN);
+ w.set_opaen(true);
});
OpAmpOutput {
_inner: self,
- _input: pin,
+ _output: out_pin,
}
}
+
+ /// Configure the OpAmp as a buffer for the provided input pin,
+ /// with the output only used internally.
+ ///
+ /// The input pin is configured for analogue mode but not consumed,
+ /// so it may be subsequently used for ADC or comparator inputs.
+ ///
+ /// The returned `OpAmpInternalOutput` struct may be used as an ADC input.
+ #[cfg(opamp_g4)]
+ pub fn buffer_int<'a, P>(&'a mut self, pin: &P, gain: OpAmpGain) -> OpAmpInternalOutput<'a, T>
+ where
+ P: NonInvertingPin + crate::gpio::sealed::Pin,
+ {
+ pin.set_as_analog();
+
+ let (vm_sel, pga_gain) = match gain {
+ OpAmpGain::Mul1 => (0b11, 0b00),
+ OpAmpGain::Mul2 => (0b10, 0b00),
+ OpAmpGain::Mul4 => (0b10, 0b01),
+ OpAmpGain::Mul8 => (0b10, 0b10),
+ OpAmpGain::Mul16 => (0b10, 0b11),
+ };
+
+ T::regs().opamp_csr().modify(|w| {
+ use crate::pac::opamp::vals::*;
+ w.set_vp_sel(OpampCsrVpSel::from_bits(pin.channel()));
+ w.set_vm_sel(OpampCsrVmSel::from_bits(vm_sel));
+ w.set_pga_gain(OpampCsrPgaGain::from_bits(pga_gain));
+ w.set_opaintoen(OpampCsrOpaintoen::ADCCHANNEL);
+ w.set_opaen(true);
+ });
+
+ OpAmpInternalOutput { _inner: self }
+ }
+}
+
+impl<'d, T: Instance> Drop for OpAmp<'d, T> {
+ fn drop(&mut self) {
+ #[cfg(opamp_f3)]
+ T::regs().opampcsr().modify(|w| {
+ w.set_opampen(false);
+ });
+
+ #[cfg(opamp_g4)]
+ T::regs().opamp_csr().modify(|w| {
+ w.set_opaen(false);
+ });
+ }
}
pub trait Instance: sealed::Instance + 'static {}
@@ -92,18 +191,19 @@ pub(crate) mod sealed {
pub trait InvertingPin {
fn channel(&self) -> u8;
}
+
+ pub trait OutputPin {}
}
pub trait NonInvertingPin: sealed::NonInvertingPin {}
-
pub trait InvertingPin: sealed::InvertingPin {}
+pub trait OutputPin: sealed::OutputPin {}
-#[cfg(opamp_f3)]
-macro_rules! impl_opamp_output {
+macro_rules! impl_opamp_external_output {
($inst:ident, $adc:ident, $ch:expr) => {
foreach_adc!(
($adc, $common_inst:ident, $adc_clock:ident) => {
- impl<'d, 'p, P: NonInvertingPin> crate::adc::sealed::AdcPin
+ impl<'d, 'p, P: OutputPin> crate::adc::sealed::AdcPin
for OpAmpOutput<'d, 'p, crate::peripherals::$inst, P>
{
fn channel(&self) -> u8 {
@@ -111,7 +211,7 @@ macro_rules! impl_opamp_output {
}
}
- impl<'d, 'p, P: NonInvertingPin> crate::adc::AdcPin
+ impl<'d, 'p, P: OutputPin> crate::adc::AdcPin
for OpAmpOutput<'d, 'p, crate::peripherals::$inst, P>
{
}
@@ -120,19 +220,79 @@ macro_rules! impl_opamp_output {
};
}
-#[cfg(opamp_f3)]
foreach_peripheral!(
(opamp, OPAMP1) => {
- impl_opamp_output!(OPAMP1, ADC1, 3);
+ impl_opamp_external_output!(OPAMP1, ADC1, 3);
};
(opamp, OPAMP2) => {
- impl_opamp_output!(OPAMP2, ADC2, 3);
+ impl_opamp_external_output!(OPAMP2, ADC2, 3);
};
(opamp, OPAMP3) => {
- impl_opamp_output!(OPAMP3, ADC3, 1);
+ impl_opamp_external_output!(OPAMP3, ADC3, 1);
};
+ // OPAMP4 only in STM32G4 Cat 3 devices
(opamp, OPAMP4) => {
- impl_opamp_output!(OPAMP4, ADC4, 3);
+ impl_opamp_external_output!(OPAMP4, ADC4, 3);
+ };
+ // OPAMP5 only in STM32G4 Cat 3 devices
+ (opamp, OPAMP5) => {
+ impl_opamp_external_output!(OPAMP5, ADC5, 1);
+ };
+ // OPAMP6 only in STM32G4 Cat 3/4 devices
+ (opamp, OPAMP6) => {
+ impl_opamp_external_output!(OPAMP6, ADC1, 14);
+ };
+);
+
+#[cfg(opamp_g4)]
+macro_rules! impl_opamp_internal_output {
+ ($inst:ident, $adc:ident, $ch:expr) => {
+ foreach_adc!(
+ ($adc, $common_inst:ident, $adc_clock:ident) => {
+ impl<'d> crate::adc::sealed::AdcPin
+ for OpAmpInternalOutput<'d, crate::peripherals::$inst>
+ {
+ fn channel(&self) -> u8 {
+ $ch
+ }
+ }
+
+ impl<'d> crate::adc::AdcPin
+ for OpAmpInternalOutput<'d, crate::peripherals::$inst>
+ {
+ }
+ };
+ );
+ };
+}
+
+#[cfg(opamp_g4)]
+foreach_peripheral!(
+ (opamp, OPAMP1) => {
+ impl_opamp_internal_output!(OPAMP1, ADC1, 13);
+ };
+ (opamp, OPAMP2) => {
+ impl_opamp_internal_output!(OPAMP2, ADC2, 16);
+ };
+ (opamp, OPAMP3) => {
+ impl_opamp_internal_output!(OPAMP3, ADC2, 18);
+ // Only in Cat 3/4 devices
+ impl_opamp_internal_output!(OPAMP3, ADC3, 13);
+ };
+ // OPAMP4 only in Cat 3 devices
+ (opamp, OPAMP4) => {
+ impl_opamp_internal_output!(OPAMP4, ADC5, 5);
+ };
+ // OPAMP5 only in Cat 3 devices
+ (opamp, OPAMP5) => {
+ impl_opamp_internal_output!(OPAMP5, ADC5, 3);
+ };
+ // OPAMP6 only in Cat 3/4 devices
+ (opamp, OPAMP6) => {
+ // Only in Cat 3 devices
+ impl_opamp_internal_output!(OPAMP6, ADC4, 17);
+ // Only in Cat 4 devices
+ impl_opamp_internal_output!(OPAMP6, ADC3, 17);
};
);
@@ -145,13 +305,12 @@ foreach_peripheral! {
}
impl Instance for crate::peripherals::$inst {
-
}
};
}
#[allow(unused_macros)]
-macro_rules! impl_opamp_pin {
+macro_rules! impl_opamp_vp_pin {
($inst:ident, $pin:ident, $ch:expr) => {
impl crate::opamp::NonInvertingPin for crate::peripherals::$pin {}
impl crate::opamp::sealed::NonInvertingPin for crate::peripherals::$pin {
@@ -161,3 +320,11 @@ macro_rules! impl_opamp_pin {
}
};
}
+
+#[allow(unused_macros)]
+macro_rules! impl_opamp_vout_pin {
+ ($inst:ident, $pin:ident) => {
+ impl crate::opamp::OutputPin for crate::peripherals::$pin {}
+ impl crate::opamp::sealed::OutputPin for crate::peripherals::$pin {}
+ };
+}
diff --git a/embassy-stm32/src/rcc/f4f7.rs b/embassy-stm32/src/rcc/f4f7.rs
index 2e4f9572..9e8c639d 100644
--- a/embassy-stm32/src/rcc/f4f7.rs
+++ b/embassy-stm32/src/rcc/f4f7.rs
@@ -1,8 +1,9 @@
+use crate::pac::pwr::vals::Vos;
pub use crate::pac::rcc::vals::{
Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp, Pllq, Pllr, Pllsrc as PllSource,
Ppre as APBPrescaler, Sw as Sysclk,
};
-use crate::pac::{FLASH, RCC};
+use crate::pac::{FLASH, PWR, RCC};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
@@ -100,12 +101,17 @@ impl Default for Config {
}
pub(crate) unsafe fn init(config: Config) {
+ // set VOS to SCALE1, if use PLL
+ // TODO: check real clock speed before set VOS
+ if config.pll.is_some() {
+ PWR.cr1().modify(|w| w.set_vos(Vos::SCALE1));
+ }
+
// always enable overdrive for now. Make it configurable in the future.
#[cfg(not(any(
stm32f401, stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f405, stm32f407, stm32f415, stm32f417
)))]
{
- use crate::pac::PWR;
PWR.cr1().modify(|w| w.set_oden(true));
while !PWR.csr1().read().odrdy() {}
diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs
index b14a6197..13eb0c48 100644
--- a/embassy-stm32/src/rcc/g4.rs
+++ b/embassy-stm32/src/rcc/g4.rs
@@ -7,7 +7,6 @@ pub use crate::pac::rcc::vals::{
Pllr as PllR, Ppre as APBPrescaler,
};
use crate::pac::{PWR, RCC};
-use crate::rcc::sealed::RccPeripheral;
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
@@ -67,23 +66,13 @@ pub struct Pll {
pub enum Clock48MhzSrc {
/// Use the High Speed Internal Oscillator. For USB usage, the CRS must be used to calibrate the
/// oscillator to comply with the USB specification for oscillator tolerance.
- Hsi48(Option),
+ Hsi48(super::Hsi48Config),
/// Use the PLLQ output. The PLL must be configured to output a 48MHz clock. For USB usage the
/// PLL needs to be using the HSE source to comply with the USB specification for oscillator
/// tolerance.
PllQ,
}
-/// Sets the sync source for the Clock Recovery System (CRS).
-pub enum CrsSyncSource {
- /// Use an external GPIO to sync the CRS.
- Gpio,
- /// Use the Low Speed External oscillator to sync the CRS.
- Lse,
- /// Use the USB SOF to sync the CRS.
- Usb,
-}
-
/// Clocks configutation
pub struct Config {
pub mux: ClockSrc,
@@ -102,12 +91,6 @@ pub struct Config {
pub ls: super::LsConfig,
}
-/// Configuration for the Clock Recovery System (CRS) used to trim the HSI48 oscillator.
-pub struct CrsConfig {
- /// Sync source for the CRS.
- pub sync_src: CrsSyncSource,
-}
-
impl Default for Config {
#[inline]
fn default() -> Config {
@@ -118,7 +101,7 @@ impl Default for Config {
apb2_pre: APBPrescaler::DIV1,
low_power_run: false,
pll: None,
- clock_48mhz_src: Some(Clock48MhzSrc::Hsi48(None)),
+ clock_48mhz_src: Some(Clock48MhzSrc::Hsi48(Default::default())),
adc12_clock_source: Adcsel::DISABLE,
adc345_clock_source: Adcsel::DISABLE,
ls: Default::default(),
@@ -288,33 +271,8 @@ pub(crate) unsafe fn init(config: Config) {
crate::pac::rcc::vals::Clk48sel::PLL1_Q
}
- Clock48MhzSrc::Hsi48(crs_config) => {
- // Enable HSI48
- RCC.crrcr().modify(|w| w.set_hsi48on(true));
- // Wait for HSI48 to turn on
- while RCC.crrcr().read().hsi48rdy() == false {}
-
- // Enable and setup CRS if needed
- if let Some(crs_config) = crs_config {
- crate::peripherals::CRS::enable_and_reset();
-
- let sync_src = match crs_config.sync_src {
- CrsSyncSource::Gpio => crate::pac::crs::vals::Syncsrc::GPIO,
- CrsSyncSource::Lse => crate::pac::crs::vals::Syncsrc::LSE,
- CrsSyncSource::Usb => crate::pac::crs::vals::Syncsrc::USB,
- };
-
- crate::pac::CRS.cfgr().modify(|w| {
- w.set_syncsrc(sync_src);
- });
-
- // These are the correct settings for standard USB operation. If other settings
- // are needed there will need to be additional config options for the CRS.
- crate::pac::CRS.cr().modify(|w| {
- w.set_autotrimen(true);
- w.set_cen(true);
- });
- }
+ Clock48MhzSrc::Hsi48(config) => {
+ super::init_hsi48(config);
crate::pac::rcc::vals::Clk48sel::HSI48
}
};
diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs
index 7e924f0a..4407d9e9 100644
--- a/embassy-stm32/src/rcc/h.rs
+++ b/embassy-stm32/src/rcc/h.rs
@@ -21,9 +21,6 @@ pub const HSI_FREQ: Hertz = Hertz(64_000_000);
/// CSI speed
pub const CSI_FREQ: Hertz = Hertz(4_000_000);
-/// HSI48 speed
-pub const HSI48_FREQ: Hertz = Hertz(48_000_000);
-
const VCO_RANGE: RangeInclusive = Hertz(150_000_000)..=Hertz(420_000_000);
#[cfg(any(stm32h5, pwr_h7rm0455))]
const VCO_WIDE_RANGE: RangeInclusive = Hertz(128_000_000)..=Hertz(560_000_000);
@@ -126,7 +123,7 @@ pub struct Config {
pub hsi: Option,
pub hse: Option,
pub csi: bool,
- pub hsi48: bool,
+ pub hsi48: Option,
pub sys: Sysclk,
pub pll1: Option,
@@ -155,7 +152,7 @@ impl Default for Config {
hsi: Some(HSIPrescaler::DIV1),
hse: None,
csi: false,
- hsi48: false,
+ hsi48: Some(Default::default()),
sys: Sysclk::HSI,
pll1: None,
pll2: None,
@@ -301,14 +298,7 @@ pub(crate) unsafe fn init(config: Config) {
};
// Configure HSI48.
- RCC.cr().modify(|w| w.set_hsi48on(config.hsi48));
- let _hsi48 = match config.hsi48 {
- false => None,
- true => {
- while !RCC.cr().read().hsi48rdy() {}
- Some(CSI_FREQ)
- }
- };
+ let _hsi48 = config.hsi48.map(super::init_hsi48);
// Configure CSI.
RCC.cr().modify(|w| w.set_csion(config.csi));
diff --git a/embassy-stm32/src/rcc/hsi48.rs b/embassy-stm32/src/rcc/hsi48.rs
new file mode 100644
index 00000000..19a8c8cb
--- /dev/null
+++ b/embassy-stm32/src/rcc/hsi48.rs
@@ -0,0 +1,62 @@
+#![allow(unused)]
+
+use crate::pac::crs::vals::Syncsrc;
+use crate::pac::{CRS, RCC};
+use crate::rcc::sealed::RccPeripheral;
+use crate::time::Hertz;
+
+/// HSI48 speed
+pub const HSI48_FREQ: Hertz = Hertz(48_000_000);
+
+/// Configuration for the HSI48 clock
+#[derive(Clone, Copy, Debug)]
+pub struct Hsi48Config {
+ /// Enable CRS Sync from USB Start Of Frame (SOF) events.
+ /// Required if HSI48 is going to be used as USB clock.
+ ///
+ /// Other use cases of CRS are not supported yet.
+ pub sync_from_usb: bool,
+}
+
+impl Default for Hsi48Config {
+ fn default() -> Self {
+ Self { sync_from_usb: false }
+ }
+}
+
+pub(crate) fn init_hsi48(config: Hsi48Config) -> Hertz {
+ // Enable VREFINT reference for HSI48 oscillator
+ #[cfg(stm32l0)]
+ crate::pac::SYSCFG.cfgr3().modify(|w| {
+ w.set_enref_hsi48(true);
+ w.set_en_vrefint(true);
+ });
+
+ // Enable HSI48
+ #[cfg(not(any(stm32u5, stm32g0, stm32h5, stm32h7, stm32u5, stm32wba, stm32f0)))]
+ let r = RCC.crrcr();
+ #[cfg(any(stm32u5, stm32g0, stm32h5, stm32h7, stm32u5, stm32wba))]
+ let r = RCC.cr();
+ #[cfg(any(stm32f0))]
+ let r = RCC.cr2();
+
+ r.modify(|w| w.set_hsi48on(true));
+ while r.read().hsi48rdy() == false {}
+
+ if config.sync_from_usb {
+ crate::peripherals::CRS::enable_and_reset();
+
+ CRS.cfgr().modify(|w| {
+ w.set_syncsrc(Syncsrc::USB);
+ });
+
+ // These are the correct settings for standard USB operation. If other settings
+ // are needed there will need to be additional config options for the CRS.
+ crate::pac::CRS.cr().modify(|w| {
+ w.set_autotrimen(true);
+ w.set_cen(true);
+ });
+ }
+
+ HSI48_FREQ
+}
diff --git a/embassy-stm32/src/rcc/l0l1.rs b/embassy-stm32/src/rcc/l0l1.rs
index 3af27959..25a7762a 100644
--- a/embassy-stm32/src/rcc/l0l1.rs
+++ b/embassy-stm32/src/rcc/l0l1.rs
@@ -3,8 +3,6 @@ pub use crate::pac::rcc::vals::{
Hpre as AHBPrescaler, Msirange as MSIRange, Plldiv as PLLDiv, Plldiv as PllDiv, Pllmul as PLLMul, Pllmul as PllMul,
Pllsrc as PLLSource, Ppre as APBPrescaler, Sw as ClockSrc,
};
-#[cfg(crs)]
-use crate::pac::{crs, CRS, SYSCFG};
use crate::pac::{FLASH, PWR, RCC};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
@@ -47,7 +45,7 @@ pub struct Config {
pub hsi: bool,
pub hse: Option,
#[cfg(crs)]
- pub hsi48: bool,
+ pub hsi48: Option,
pub pll: Option,
@@ -68,7 +66,7 @@ impl Default for Config {
hse: None,
hsi: false,
#[cfg(crs)]
- hsi48: false,
+ hsi48: Some(Default::default()),
pll: None,
@@ -174,37 +172,11 @@ pub(crate) unsafe fn init(config: Config) {
let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk1, config.apb2_pre);
#[cfg(crs)]
- if config.hsi48 {
- // Reset CRS peripheral
- RCC.apb1rstr().modify(|w| w.set_crsrst(true));
- RCC.apb1rstr().modify(|w| w.set_crsrst(false));
-
- // Enable CRS peripheral
- RCC.apb1enr().modify(|w| w.set_crsen(true));
-
- // Initialize CRS
- CRS.cfgr().write(|w|
-
- // Select LSE as synchronization source
- w.set_syncsrc(crs::vals::Syncsrc::LSE));
- CRS.cr().modify(|w| {
- w.set_autotrimen(true);
- w.set_cen(true);
- });
-
- // Enable VREFINT reference for HSI48 oscillator
- SYSCFG.cfgr3().modify(|w| {
- w.set_enref_hsi48(true);
- w.set_en_vrefint(true);
- });
-
+ let _hsi48 = config.hsi48.map(|config| {
// Select HSI48 as USB clock
RCC.ccipr().modify(|w| w.set_hsi48msel(true));
-
- // Enable dedicated USB clock
- RCC.crrcr().modify(|w| w.set_hsi48on(true));
- while !RCC.crrcr().read().hsi48rdy() {}
- }
+ super::init_hsi48(config)
+ });
set_freqs(Clocks {
sys: sys_clk,
diff --git a/embassy-stm32/src/rcc/l4l5.rs b/embassy-stm32/src/rcc/l4l5.rs
index 44748620..c4483910 100644
--- a/embassy-stm32/src/rcc/l4l5.rs
+++ b/embassy-stm32/src/rcc/l4l5.rs
@@ -58,8 +58,8 @@ pub struct Config {
pub msi: Option,
pub hsi: bool,
pub hse: Option,
- #[cfg(any(all(stm32l4, not(any(stm32l47x, stm32l48x))), stm32l5, stm32wb))]
- pub hsi48: bool,
+ #[cfg(crs)]
+ pub hsi48: Option,
// pll
pub pll: Option,
@@ -108,8 +108,8 @@ impl Default for Config {
pllsai1: None,
#[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
pllsai2: None,
- #[cfg(any(all(stm32l4, not(any(stm32l47x, stm32l48x))), stm32l5, stm32wb))]
- hsi48: true,
+ #[cfg(crs)]
+ hsi48: Some(Default::default()),
#[cfg(any(stm32l4, stm32l5, stm32wb))]
clk48_src: Clk48Src::HSI48,
ls: Default::default(),
@@ -126,7 +126,8 @@ pub const WPAN_DEFAULT: Config = Config {
prescaler: HsePrescaler::DIV1,
}),
mux: ClockSrc::PLL1_R,
- hsi48: true,
+ #[cfg(crs)]
+ hsi48: Some(super::Hsi48Config { sync_from_usb: false }),
msi: None,
hsi: false,
clk48_src: Clk48Src::PLL1_Q,
@@ -216,15 +217,10 @@ pub(crate) unsafe fn init(config: Config) {
hse.freq
});
- #[cfg(any(all(stm32l4, not(any(stm32l47x, stm32l48x))), stm32l5, stm32wb))]
- let hsi48 = config.hsi48.then(|| {
- RCC.crrcr().modify(|w| w.set_hsi48on(true));
- while !RCC.crrcr().read().hsi48rdy() {}
-
- Hertz(48_000_000)
- });
- #[cfg(any(stm32l47x, stm32l48x))]
- let hsi48 = None;
+ #[cfg(crs)]
+ let _hsi48 = config.hsi48.map(super::init_hsi48);
+ #[cfg(not(crs))]
+ let _hsi48: Option = None;
let _plls = [
&config.pll,
@@ -275,7 +271,7 @@ pub(crate) unsafe fn init(config: Config) {
RCC.ccipr1().modify(|w| w.set_clk48sel(config.clk48_src));
#[cfg(any(stm32l4, stm32l5, stm32wb))]
let _clk48 = match config.clk48_src {
- Clk48Src::HSI48 => hsi48,
+ Clk48Src::HSI48 => _hsi48,
Clk48Src::MSI => msi,
Clk48Src::PLLSAI1_Q => pllsai1.q,
Clk48Src::PLL1_Q => pll.q,
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index c11a9cc6..e15f4fe4 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -9,6 +9,11 @@ mod mco;
pub use bd::*;
pub use mco::*;
+#[cfg(crs)]
+mod hsi48;
+#[cfg(crs)]
+pub use hsi48::*;
+
#[cfg_attr(rcc_f0, path = "f0.rs")]
#[cfg_attr(any(rcc_f1, rcc_f100, rcc_f1cl), path = "f1.rs")]
#[cfg_attr(rcc_f2, path = "f2.rs")]
diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs
index 2bbacbbd..c111362b 100644
--- a/embassy-stm32/src/rcc/u5.rs
+++ b/embassy-stm32/src/rcc/u5.rs
@@ -115,7 +115,7 @@ pub struct Config {
pub apb1_pre: APBPrescaler,
pub apb2_pre: APBPrescaler,
pub apb3_pre: APBPrescaler,
- pub hsi48: bool,
+ pub hsi48: Option,
/// The voltage range influences the maximum clock frequencies for different parts of the
/// device. In particular, system clocks exceeding 110 MHz require `RANGE1`, and system clocks
/// exceeding 55 MHz require at least `RANGE2`.
@@ -189,7 +189,7 @@ impl Default for Config {
apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1,
apb3_pre: APBPrescaler::DIV1,
- hsi48: true,
+ hsi48: Some(Default::default()),
voltage_range: VoltageScale::RANGE3,
ls: Default::default(),
}
@@ -322,10 +322,7 @@ pub(crate) unsafe fn init(config: Config) {
}
};
- if config.hsi48 {
- RCC.cr().modify(|w| w.set_hsi48on(true));
- while !RCC.cr().read().hsi48rdy() {}
- }
+ let _hsi48 = config.hsi48.map(super::init_hsi48);
// The clock source is ready
// Calculate and set the flash wait states
diff --git a/embassy-stm32/src/rtc/mod.rs b/embassy-stm32/src/rtc/mod.rs
index e94a5857..b4315f53 100644
--- a/embassy-stm32/src/rtc/mod.rs
+++ b/embassy-stm32/src/rtc/mod.rs
@@ -33,6 +33,61 @@ use embassy_hal_internal::Peripheral;
use crate::peripherals::RTC;
use crate::rtc::sealed::Instance;
+#[allow(dead_code)]
+#[repr(u8)]
+#[derive(Clone, Copy, Debug)]
+pub(crate) enum WakeupPrescaler {
+ Div2 = 2,
+ Div4 = 4,
+ Div8 = 8,
+ Div16 = 16,
+}
+
+#[cfg(any(stm32wb, stm32f4, stm32l0, stm32g4))]
+impl From for crate::pac::rtc::vals::Wucksel {
+ fn from(val: WakeupPrescaler) -> Self {
+ use crate::pac::rtc::vals::Wucksel;
+
+ match val {
+ WakeupPrescaler::Div2 => Wucksel::DIV2,
+ WakeupPrescaler::Div4 => Wucksel::DIV4,
+ WakeupPrescaler::Div8 => Wucksel::DIV8,
+ WakeupPrescaler::Div16 => Wucksel::DIV16,
+ }
+ }
+}
+
+#[cfg(any(stm32wb, stm32f4, stm32l0, stm32g4))]
+impl From for WakeupPrescaler {
+ fn from(val: crate::pac::rtc::vals::Wucksel) -> Self {
+ use crate::pac::rtc::vals::Wucksel;
+
+ match val {
+ Wucksel::DIV2 => WakeupPrescaler::Div2,
+ Wucksel::DIV4 => WakeupPrescaler::Div4,
+ Wucksel::DIV8 => WakeupPrescaler::Div8,
+ Wucksel::DIV16 => WakeupPrescaler::Div16,
+ _ => unreachable!(),
+ }
+ }
+}
+
+#[cfg(feature = "low-power")]
+impl WakeupPrescaler {
+ pub fn compute_min(val: u32) -> Self {
+ *[
+ WakeupPrescaler::Div2,
+ WakeupPrescaler::Div4,
+ WakeupPrescaler::Div8,
+ WakeupPrescaler::Div16,
+ ]
+ .iter()
+ .skip_while(|psc| **psc as u32 <= val)
+ .next()
+ .unwrap_or(&WakeupPrescaler::Div16)
+ }
+}
+
/// Errors that can occur on methods on [RtcClock]
#[non_exhaustive]
#[derive(Clone, Debug, PartialEq, Eq)]
@@ -277,6 +332,114 @@ impl Rtc {
pub fn write_backup_register(&self, register: usize, value: u32) {
RTC::write_backup_register(&RTC::regs(), register, value)
}
+
+ #[cfg(feature = "low-power")]
+ /// start the wakeup alarm and wtih a duration that is as close to but less than
+ /// the requested duration, and record the instant the wakeup alarm was started
+ pub(crate) fn start_wakeup_alarm(
+ &self,
+ requested_duration: embassy_time::Duration,
+ cs: critical_section::CriticalSection,
+ ) {
+ use embassy_time::{Duration, TICK_HZ};
+
+ #[cfg(any(rtc_v3, rtc_v3u5))]
+ use crate::pac::rtc::vals::Calrf;
+
+ // Panic if the rcc mod knows we're not using low-power rtc
+ #[cfg(any(rcc_wb, rcc_f4, rcc_f410))]
+ unsafe { crate::rcc::get_freqs() }.rtc.unwrap();
+
+ let requested_duration = requested_duration.as_ticks().clamp(0, u32::MAX as u64);
+ let rtc_hz = Self::frequency().0 as u64;
+ let rtc_ticks = requested_duration * rtc_hz / TICK_HZ;
+ let prescaler = WakeupPrescaler::compute_min((rtc_ticks / u16::MAX as u64) as u32);
+
+ // adjust the rtc ticks to the prescaler and subtract one rtc tick
+ let rtc_ticks = rtc_ticks / prescaler as u64;
+ let rtc_ticks = rtc_ticks.clamp(0, (u16::MAX - 1) as u64).saturating_sub(1) as u16;
+
+ self.write(false, |regs| {
+ regs.cr().modify(|w| w.set_wute(false));
+
+ #[cfg(any(
+ rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb
+ ))]
+ {
+ regs.isr().modify(|w| w.set_wutf(false));
+ while !regs.isr().read().wutwf() {}
+ }
+
+ #[cfg(any(rtc_v3, rtc_v3u5))]
+ {
+ regs.scr().write(|w| w.set_cwutf(Calrf::CLEAR));
+ while !regs.icsr().read().wutwf() {}
+ }
+
+ regs.cr().modify(|w| w.set_wucksel(prescaler.into()));
+ regs.wutr().write(|w| w.set_wut(rtc_ticks));
+ regs.cr().modify(|w| w.set_wute(true));
+ regs.cr().modify(|w| w.set_wutie(true));
+ });
+
+ let instant = self.instant().unwrap();
+ trace!(
+ "rtc: start wakeup alarm for {} ms (psc: {}, ticks: {}) at {}",
+ Duration::from_ticks(rtc_ticks as u64 * TICK_HZ * prescaler as u64 / rtc_hz).as_millis(),
+ prescaler as u32,
+ rtc_ticks,
+ instant,
+ );
+
+ assert!(self.stop_time.borrow(cs).replace(Some(instant)).is_none())
+ }
+
+ #[cfg(feature = "low-power")]
+ /// stop the wakeup alarm and return the time elapsed since `start_wakeup_alarm`
+ /// was called, otherwise none
+ pub(crate) fn stop_wakeup_alarm(&self, cs: critical_section::CriticalSection) -> Option {
+ use crate::interrupt::typelevel::Interrupt;
+ #[cfg(any(rtc_v3, rtc_v3u5))]
+ use crate::pac::rtc::vals::Calrf;
+
+ let instant = self.instant().unwrap();
+ if RTC::regs().cr().read().wute() {
+ trace!("rtc: stop wakeup alarm at {}", instant);
+
+ self.write(false, |regs| {
+ regs.cr().modify(|w| w.set_wutie(false));
+ regs.cr().modify(|w| w.set_wute(false));
+
+ #[cfg(any(
+ rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb
+ ))]
+ regs.isr().modify(|w| w.set_wutf(false));
+
+ #[cfg(any(rtc_v3, rtc_v3u5))]
+ regs.scr().write(|w| w.set_cwutf(Calrf::CLEAR));
+
+ crate::pac::EXTI
+ .pr(0)
+ .modify(|w| w.set_line(RTC::EXTI_WAKEUP_LINE, true));
+
+