Merge #526
526: stm32/usart: unify v1 and v2 r=Dirbaio a=Dirbaio Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
This commit is contained in:
bors[bot]
GitHub
commit
1c651e2b44
@ -1,14 +1,18 @@
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#![macro_use]
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#[cfg_attr(usart_v1, path = "v1.rs")]
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#[cfg_attr(usart_v2, path = "v2.rs")]
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mod _version;
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use crate::{dma, peripherals};
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pub use _version::*;
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use crate::gpio::Pin;
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use crate::rcc::RccPeripheral;
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use core::future::Future;
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use core::marker::PhantomData;
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use embassy::interrupt::Interrupt;
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use embassy::util::Unborrow;
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use embassy_hal_common::unborrow;
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use futures::TryFutureExt;
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use crate::dma::NoDma;
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use crate::gpio::sealed::AFType::{OutputOpenDrain, OutputPushPull};
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use crate::gpio::Pin;
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use crate::pac::usart::{regs, vals};
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use crate::rcc::RccPeripheral;
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use crate::{dma, peripherals};
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#[derive(Clone, Copy, PartialEq, Eq, Debug)]
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pub enum DataBits {
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@ -70,6 +74,414 @@ pub enum Error {
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Parity,
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}
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pub struct Uart<'d, T: Instance, TxDma = NoDma, RxDma = NoDma> {
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inner: T,
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phantom: PhantomData<&'d mut T>,
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tx_dma: TxDma,
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rx_dma: RxDma,
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}
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impl<'d, T: Instance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
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pub fn new(
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inner: impl Unborrow<Target = T>,
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rx: impl Unborrow<Target = impl RxPin<T>>,
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tx: impl Unborrow<Target = impl TxPin<T>>,
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tx_dma: impl Unborrow<Target = TxDma>,
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rx_dma: impl Unborrow<Target = RxDma>,
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config: Config,
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) -> Self {
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unborrow!(inner, rx, tx, tx_dma, rx_dma);
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T::enable();
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let pclk_freq = T::frequency();
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// TODO: better calculation, including error checking and OVER8 if possible.
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let div = (pclk_freq.0 + (config.baudrate / 2)) / config.baudrate;
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let r = inner.regs();
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unsafe {
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rx.set_as_af(rx.af_num(), OutputOpenDrain);
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tx.set_as_af(tx.af_num(), OutputPushPull);
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r.cr2().write(|_w| {});
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r.cr3().write(|_w| {});
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r.brr().write_value(regs::Brr(div));
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r.cr1().write(|w| {
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w.set_ue(true);
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w.set_te(true);
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w.set_re(true);
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w.set_m0(vals::M0::BIT8);
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w.set_pce(config.parity != Parity::ParityNone);
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w.set_ps(match config.parity {
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Parity::ParityOdd => vals::Ps::ODD,
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Parity::ParityEven => vals::Ps::EVEN,
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_ => vals::Ps::EVEN,
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});
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});
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}
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Self {
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inner,
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phantom: PhantomData,
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tx_dma,
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rx_dma,
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}
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}
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async fn write_dma(&mut self, buffer: &[u8]) -> Result<(), Error>
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where
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TxDma: crate::usart::TxDma<T>,
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{
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let ch = &mut self.tx_dma;
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let request = ch.request();
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unsafe {
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self.inner.regs().cr3().modify(|reg| {
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reg.set_dmat(true);
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});
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}
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let r = self.inner.regs();
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let dst = tdr(r);
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crate::dma::write(ch, request, buffer, dst).await;
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Ok(())
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}
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async fn read_dma(&mut self, buffer: &mut [u8]) -> Result<(), Error>
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where
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RxDma: crate::usart::RxDma<T>,
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{
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let ch = &mut self.rx_dma;
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let request = ch.request();
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unsafe {
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self.inner.regs().cr3().modify(|reg| {
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reg.set_dmar(true);
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});
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}
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let r = self.inner.regs();
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let src = rdr(r);
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crate::dma::read(ch, request, src, buffer).await;
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Ok(())
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}
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pub fn read_blocking(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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unsafe {
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let r = self.inner.regs();
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for b in buffer {
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loop {
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let sr = sr(r).read();
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if sr.pe() {
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rdr(r).read_volatile();
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return Err(Error::Parity);
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} else if sr.fe() {
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rdr(r).read_volatile();
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return Err(Error::Framing);
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} else if sr.ne() {
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rdr(r).read_volatile();
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return Err(Error::Noise);
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} else if sr.ore() {
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rdr(r).read_volatile();
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return Err(Error::Overrun);
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} else if sr.rxne() {
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break;
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}
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}
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*b = rdr(r).read_volatile();
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}
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}
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Ok(())
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}
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}
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impl<'d, T: Instance, RxDma> embedded_hal::blocking::serial::Write<u8>
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for Uart<'d, T, NoDma, RxDma>
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{
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type Error = Error;
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fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
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unsafe {
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let r = self.inner.regs();
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for &b in buffer {
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while !sr(r).read().txe() {}
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tdr(r).write_volatile(b);
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}
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}
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Ok(())
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}
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fn bflush(&mut self) -> Result<(), Self::Error> {
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unsafe {
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let r = self.inner.regs();
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while !sr(r).read().tc() {}
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}
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Ok(())
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}
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}
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impl<'d, T: Instance, TxDma, RxDma> embassy_traits::uart::Write for Uart<'d, T, TxDma, RxDma>
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where
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TxDma: crate::usart::TxDma<T>,
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{
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#[rustfmt::skip]
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type WriteFuture<'a> where Self: 'a = impl Future<Output = Result<(), embassy_traits::uart::Error>> + 'a;
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fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
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self.write_dma(buf)
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.map_err(|_| embassy_traits::uart::Error::Other)
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}
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}
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impl<'d, T: Instance, TxDma, RxDma> embassy_traits::uart::Read for Uart<'d, T, TxDma, RxDma>
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where
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RxDma: crate::usart::RxDma<T>,
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{
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#[rustfmt::skip]
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type ReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), embassy_traits::uart::Error>> + 'a;
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fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
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self.read_dma(buf)
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.map_err(|_| embassy_traits::uart::Error::Other)
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}
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}
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#[cfg(usart_v2)]
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pub use buffered::*;
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#[cfg(usart_v2)]
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mod buffered {
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use atomic_polyfill::{compiler_fence, Ordering};
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use core::pin::Pin;
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use core::task::Context;
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use core::task::Poll;
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use embassy::waitqueue::WakerRegistration;
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use embassy_hal_common::peripheral::{PeripheralMutex, PeripheralState, StateStorage};
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use embassy_hal_common::ring_buffer::RingBuffer;
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use super::*;
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pub struct State<'d, T: Instance>(StateStorage<StateInner<'d, T>>);
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impl<'d, T: Instance> State<'d, T> {
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pub fn new() -> Self {
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Self(StateStorage::new())
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}
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}
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struct StateInner<'d, T: Instance> {
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uart: Uart<'d, T, NoDma, NoDma>,
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phantom: PhantomData<&'d mut T>,
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rx_waker: WakerRegistration,
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rx: RingBuffer<'d>,
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tx_waker: WakerRegistration,
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tx: RingBuffer<'d>,
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}
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unsafe impl<'d, T: Instance> Send for StateInner<'d, T> {}
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unsafe impl<'d, T: Instance> Sync for StateInner<'d, T> {}
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pub struct BufferedUart<'d, T: Instance> {
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inner: PeripheralMutex<'d, StateInner<'d, T>>,
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}
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impl<'d, T: Instance> Unpin for BufferedUart<'d, T> {}
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impl<'d, T: Instance> BufferedUart<'d, T> {
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pub unsafe fn new(
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state: &'d mut State<'d, T>,
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uart: Uart<'d, T, NoDma, NoDma>,
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irq: impl Unborrow<Target = T::Interrupt> + 'd,
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tx_buffer: &'d mut [u8],
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rx_buffer: &'d mut [u8],
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) -> BufferedUart<'d, T> {
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unborrow!(irq);
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let r = uart.inner.regs();
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r.cr1().modify(|w| {
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w.set_rxneie(true);
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w.set_idleie(true);
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});
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Self {
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inner: PeripheralMutex::new_unchecked(irq, &mut state.0, move || StateInner {
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uart,
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phantom: PhantomData,
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tx: RingBuffer::new(tx_buffer),
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tx_waker: WakerRegistration::new(),
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rx: RingBuffer::new(rx_buffer),
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rx_waker: WakerRegistration::new(),
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}),
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}
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}
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}
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impl<'d, T: Instance> StateInner<'d, T>
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where
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Self: 'd,
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{
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fn on_rx(&mut self) {
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let r = self.uart.inner.regs();
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unsafe {
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let sr = r.isr().read();
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if sr.pe() {
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r.icr().write(|w| {
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w.set_pe(true);
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});
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trace!("Parity error");
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} else if sr.fe() {
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r.icr().write(|w| {
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w.set_fe(true);
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});
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trace!("Framing error");
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} else if sr.ne() {
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r.icr().write(|w| {
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w.set_ne(true);
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});
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trace!("Noise error");
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} else if sr.ore() {
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r.icr().write(|w| {
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w.set_ore(true);
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});
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trace!("Overrun error");
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} else if sr.rxne() {
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let buf = self.rx.push_buf();
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if buf.is_empty() {
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self.rx_waker.wake();
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} else {
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buf[0] = r.rdr().read().0 as u8;
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self.rx.push(1);
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}
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} else if sr.idle() {
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r.icr().write(|w| {
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w.set_idle(true);
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});
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self.rx_waker.wake();
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};
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}
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}
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fn on_tx(&mut self) {
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let r = self.uart.inner.regs();
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unsafe {
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if r.isr().read().txe() {
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let buf = self.tx.pop_buf();
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if !buf.is_empty() {
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r.cr1().modify(|w| {
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w.set_txeie(true);
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});
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r.tdr().write_value(regs::Dr(buf[0].into()));
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self.tx.pop(1);
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self.tx_waker.wake();
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} else {
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// Disable interrupt until we have something to transmit again
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r.cr1().modify(|w| {
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w.set_txeie(false);
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});
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}
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}
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}
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}
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}
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impl<'d, T: Instance> PeripheralState for StateInner<'d, T>
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where
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Self: 'd,
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{
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type Interrupt = T::Interrupt;
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fn on_interrupt(&mut self) {
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self.on_rx();
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self.on_tx();
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}
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}
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impl<'d, T: Instance> embassy::io::AsyncBufRead for BufferedUart<'d, T> {
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fn poll_fill_buf(
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mut self: Pin<&mut Self>,
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cx: &mut Context<'_>,
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) -> Poll<Result<&[u8], embassy::io::Error>> {
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self.inner.with(|state| {
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compiler_fence(Ordering::SeqCst);
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// We have data ready in buffer? Return it.
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let buf = state.rx.pop_buf();
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if !buf.is_empty() {
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let buf: &[u8] = buf;
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// Safety: buffer lives as long as uart
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let buf: &[u8] = unsafe { core::mem::transmute(buf) };
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return Poll::Ready(Ok(buf));
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}
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state.rx_waker.register(cx.waker());
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Poll::<Result<&[u8], embassy::io::Error>>::Pending
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})
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}
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fn consume(mut self: Pin<&mut Self>, amt: usize) {
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let signal = self.inner.with(|state| {
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let full = state.rx.is_full();
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state.rx.pop(amt);
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full
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});
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if signal {
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self.inner.pend();
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}
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}
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}
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impl<'d, T: Instance> embassy::io::AsyncWrite for BufferedUart<'d, T> {
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fn poll_write(
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mut self: Pin<&mut Self>,
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cx: &mut Context<'_>,
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buf: &[u8],
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) -> Poll<Result<usize, embassy::io::Error>> {
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let (poll, empty) = self.inner.with(|state| {
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let empty = state.tx.is_empty();
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let tx_buf = state.tx.push_buf();
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if tx_buf.is_empty() {
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state.tx_waker.register(cx.waker());
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return (Poll::Pending, empty);
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}
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let n = core::cmp::min(tx_buf.len(), buf.len());
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tx_buf[..n].copy_from_slice(&buf[..n]);
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state.tx.push(n);
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(Poll::Ready(Ok(n)), empty)
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});
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if empty {
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self.inner.pend();
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}
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poll
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}
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}
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}
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#[cfg(usart_v1)]
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fn tdr(r: crate::pac::usart::Usart) -> *mut u8 {
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r.dr().ptr() as _
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}
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#[cfg(usart_v1)]
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fn rdr(r: crate::pac::usart::Usart) -> *mut u8 {
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r.dr().ptr() as _
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}
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#[cfg(usart_v1)]
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fn sr(r: crate::pac::usart::Usart) -> crate::pac::common::Reg<regs::Sr, crate::pac::common::RW> {
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r.sr()
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}
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#[cfg(usart_v2)]
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fn tdr(r: crate::pac::usart::Usart) -> *mut u8 {
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r.tdr().ptr() as _
|
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}
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#[cfg(usart_v2)]
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fn rdr(r: crate::pac::usart::Usart) -> *mut u8 {
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r.rdr().ptr() as _
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}
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#[cfg(usart_v2)]
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fn sr(r: crate::pac::usart::Usart) -> crate::pac::common::Reg<regs::Ixr, crate::pac::common::R> {
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r.isr()
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}
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pub(crate) mod sealed {
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use super::*;
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||||
|
||||
|
||||
@ -1,176 +0,0 @@
|
||||
use crate::gpio::sealed::AFType::{OutputOpenDrain, OutputPushPull};
|
||||
use core::future::Future;
|
||||
use core::marker::PhantomData;
|
||||
use embassy::util::Unborrow;
|
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use embassy_hal_common::unborrow;
|
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use futures::TryFutureExt;
|
||||
|
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use super::*;
|
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use crate::dma::NoDma;
|
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use crate::pac::usart::{regs, vals};
|
||||
|
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pub struct Uart<'d, T: Instance, TxDma = NoDma, RxDma = NoDma> {
|
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inner: T,
|
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phantom: PhantomData<&'d mut T>,
|
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tx_dma: TxDma,
|
||||
#[allow(dead_code)]
|
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rx_dma: RxDma,
|
||||
}
|
||||
|
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impl<'d, T: Instance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
|
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pub fn new(
|
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inner: impl Unborrow<Target = T>,
|
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rx: impl Unborrow<Target = impl RxPin<T>>,
|
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tx: impl Unborrow<Target = impl TxPin<T>>,
|
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tx_dma: impl Unborrow<Target = TxDma>,
|
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rx_dma: impl Unborrow<Target = RxDma>,
|
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config: Config,
|
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) -> Self {
|
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unborrow!(inner, rx, tx, tx_dma, rx_dma);
|
||||
|
||||
T::enable();
|
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let pclk_freq = T::frequency();
|
||||
|
||||
// TODO: better calculation, including error checking and OVER8 if possible.
|
||||
let div = (pclk_freq.0 + (config.baudrate / 2)) / config.baudrate;
|
||||
|
||||
let r = inner.regs();
|
||||
|
||||
unsafe {
|
||||
rx.set_as_af(rx.af_num(), OutputOpenDrain);
|
||||
tx.set_as_af(tx.af_num(), OutputPushPull);
|
||||
|
||||
r.brr().write_value(regs::Brr(div));
|
||||
r.cr1().write(|w| {
|
||||
w.set_ue(true);
|
||||
w.set_te(true);
|
||||
w.set_re(true);
|
||||
w.set_m(vals::M::M8);
|
||||
w.set_pce(config.parity != Parity::ParityNone);
|
||||
w.set_ps(match config.parity {
|
||||
Parity::ParityOdd => vals::Ps::ODD,
|
||||
Parity::ParityEven => vals::Ps::EVEN,
|
||||
_ => vals::Ps::EVEN,
|
||||
});
|
||||
});
|
||||
r.cr2().write(|_w| {});
|
||||
r.cr3().write(|_w| {});
|
||||
}
|
||||
|
||||
Self {
|
||||
inner,
|
||||
phantom: PhantomData,
|
||||
tx_dma,
|
||||
rx_dma,
|
||||
}
|
||||
}
|
||||
|
||||
async fn write_dma(&mut self, buffer: &[u8]) -> Result<(), Error>
|
||||
where
|
||||
TxDma: crate::usart::TxDma<T>,
|
||||
{
|
||||
let ch = &mut self.tx_dma;
|
||||
let request = ch.request();
|
||||
unsafe {
|
||||
self.inner.regs().cr3().modify(|reg| {
|
||||
reg.set_dmat(true);
|
||||
});
|
||||
}
|
||||
let r = self.inner.regs();
|
||||
let dst = r.dr().ptr() as *mut u8;
|
||||
crate::dma::write(ch, request, buffer, dst).await;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
async fn read_dma(&mut self, buffer: &mut [u8]) -> Result<(), Error>
|
||||
where
|
||||
RxDma: crate::usart::RxDma<T>,
|
||||
{
|
||||
let ch = &mut self.rx_dma;
|
||||
let request = ch.request();
|
||||
unsafe {
|
||||
self.inner.regs().cr3().modify(|reg| {
|
||||
reg.set_dmar(true);
|
||||
});
|
||||
}
|
||||
let r = self.inner.regs();
|
||||
let src = r.dr().ptr() as *mut u8;
|
||||
crate::dma::read(ch, request, src, buffer).await;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn read_blocking(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
|
||||
unsafe {
|
||||
let r = self.inner.regs();
|
||||
for b in buffer {
|
||||
loop {
|
||||
let sr = r.sr().read();
|
||||
if sr.pe() {
|
||||
r.dr().read();
|
||||
return Err(Error::Parity);
|
||||
} else if sr.fe() {
|
||||
r.dr().read();
|
||||
return Err(Error::Framing);
|
||||
} else if sr.ne() {
|
||||
r.dr().read();
|
||||
return Err(Error::Noise);
|
||||
} else if sr.ore() {
|
||||
r.dr().read();
|
||||
return Err(Error::Overrun);
|
||||
} else if sr.rxne() {
|
||||
break;
|
||||
}
|
||||
}
|
||||
*b = r.dr().read().0 as u8;
|
||||
}
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance, RxDma> embedded_hal::blocking::serial::Write<u8>
|
||||
for Uart<'d, T, NoDma, RxDma>
|
||||
{
|
||||
type Error = Error;
|
||||
fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
|
||||
unsafe {
|
||||
let r = self.inner.regs();
|
||||
for &b in buffer {
|
||||
while !r.sr().read().txe() {}
|
||||
r.dr().write_value(regs::Dr(b as u32))
|
||||
}
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
fn bflush(&mut self) -> Result<(), Self::Error> {
|
||||
unsafe {
|
||||
let r = self.inner.regs();
|
||||
while !r.sr().read().tc() {}
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
// rustfmt::skip because intellij removes the 'where' claus on the associated type.
|
||||
#[rustfmt::skip]
|
||||
impl<'d, T: Instance, TxDma, RxDma> embassy_traits::uart::Write for Uart<'d, T, TxDma, RxDma>
|
||||
where TxDma: crate::usart::TxDma<T>
|
||||
{
|
||||
type WriteFuture<'a> where Self: 'a = impl Future<Output = Result<(), embassy_traits::uart::Error>> + 'a;
|
||||
|
||||
fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
|
||||
self.write_dma(buf).map_err(|_| embassy_traits::uart::Error::Other)
|
||||
}
|
||||
}
|
||||
|
||||
// rustfmt::skip because intellij removes the 'where' claus on the associated type.
|
||||
#[rustfmt::skip]
|
||||
impl<'d, T: Instance, TxDma, RxDma> embassy_traits::uart::Read for Uart<'d, T, TxDma, RxDma>
|
||||
where RxDma: crate::usart::RxDma<T>
|
||||
{
|
||||
type ReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), embassy_traits::uart::Error>> + 'a;
|
||||
|
||||
fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
|
||||
self.read_dma(buf).map_err(|_| embassy_traits::uart::Error::Other)
|
||||
}
|
||||
}
|
||||
@ -1,388 +0,0 @@
|
||||
use atomic_polyfill::{compiler_fence, Ordering};
|
||||
use core::future::Future;
|
||||
use core::marker::PhantomData;
|
||||
use core::pin::Pin;
|
||||
use core::task::Context;
|
||||
use core::task::Poll;
|
||||
use embassy::util::Unborrow;
|
||||
use embassy::waitqueue::WakerRegistration;
|
||||
use embassy_hal_common::peripheral::{PeripheralMutex, PeripheralState, StateStorage};
|
||||
use embassy_hal_common::ring_buffer::RingBuffer;
|
||||
use embassy_hal_common::unborrow;
|
||||
use futures::TryFutureExt;
|
||||
|
||||
use super::*;
|
||||
use crate::dma::NoDma;
|
||||
use crate::gpio::sealed::AFType::{OutputOpenDrain, OutputPushPull};
|
||||
use crate::pac::usart::{regs, vals};
|
||||
|
||||
pub struct Uart<'d, T: Instance, TxDma = NoDma, RxDma = NoDma> {
|
||||
inner: T,
|
||||
phantom: PhantomData<&'d mut T>,
|
||||
tx_dma: TxDma,
|
||||
rx_dma: RxDma,
|
||||
}
|
||||
|
||||
impl<'d, T: Instance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
|
||||
pub fn new(
|
||||
inner: impl Unborrow<Target = T>,
|
||||
rx: impl Unborrow<Target = impl RxPin<T>>,
|
||||
tx: impl Unborrow<Target = impl TxPin<T>>,
|
||||
tx_dma: impl Unborrow<Target = TxDma>,
|
||||
rx_dma: impl Unborrow<Target = RxDma>,
|
||||
config: Config,
|
||||
) -> Self {
|
||||
unborrow!(inner, rx, tx, tx_dma, rx_dma);
|
||||
|
||||
T::enable();
|
||||
let pclk_freq = T::frequency();
|
||||
|
||||
// TODO: better calculation, including error checking and OVER8 if possible.
|
||||
let div = (pclk_freq.0 + (config.baudrate / 2)) / config.baudrate;
|
||||
|
||||
let r = inner.regs();
|
||||
|
||||
unsafe {
|
||||
rx.set_as_af(rx.af_num(), OutputOpenDrain);
|
||||
tx.set_as_af(tx.af_num(), OutputPushPull);
|
||||
|
||||
r.cr2().write(|_w| {});
|
||||
r.cr3().write(|_w| {});
|
||||
|
||||
r.brr().write(|w| w.set_brr(div as u16));
|
||||
r.cr1().write(|w| {
|
||||
w.set_ue(true);
|
||||
w.set_te(true);
|
||||
w.set_re(true);
|
||||
w.set_m0(vals::M0::BIT8);
|
||||
w.set_m1(vals::M1::M0);
|
||||
w.set_pce(config.parity != Parity::ParityNone);
|
||||
w.set_ps(match config.parity {
|
||||
Parity::ParityOdd => vals::Ps::ODD,
|
||||
Parity::ParityEven => vals::Ps::EVEN,
|
||||
_ => vals::Ps::EVEN,
|
||||
});
|
||||
});
|
||||
r.cr2().write(|_w| {});
|
||||
r.cr3().write(|_w| {});
|
||||
}
|
||||
|
||||
Self {
|
||||
inner,
|
||||
phantom: PhantomData,
|
||||
tx_dma,
|
||||
rx_dma,
|
||||
}
|
||||
}
|
||||
|
||||
async fn write_dma(&mut self, buffer: &[u8]) -> Result<(), Error>
|
||||
where
|
||||
TxDma: crate::usart::TxDma<T>,
|
||||
{
|
||||
let ch = &mut self.tx_dma;
|
||||
let request = ch.request();
|
||||
unsafe {
|
||||
self.inner.regs().cr3().modify(|reg| {
|
||||
reg.set_dmat(true);
|
||||
});
|
||||
}
|
||||
let r = self.inner.regs();
|
||||
let dst = r.tdr().ptr() as *mut u8;
|
||||
crate::dma::write(ch, request, buffer, dst).await;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
async fn read_dma(&mut self, buffer: &mut [u8]) -> Result<(), Error>
|
||||
where
|
||||
RxDma: crate::usart::RxDma<T>,
|
||||
{
|
||||
let ch = &mut self.rx_dma;
|
||||
let request = ch.request();
|
||||
unsafe {
|
||||
self.inner.regs().cr3().modify(|reg| {
|
||||
reg.set_dmar(true);
|
||||
});
|
||||
}
|
||||
let r = self.inner.regs();
|
||||
let src = r.rdr().ptr() as *mut u8;
|
||||
|
||||
crate::dma::read(ch, request, src, buffer).await;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn read_blocking(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
|
||||
unsafe {
|
||||
let r = self.inner.regs();
|
||||
for b in buffer {
|
||||
loop {
|
||||
let sr = r.isr().read();
|
||||
if sr.pe() {
|
||||
r.rdr().read();
|
||||
return Err(Error::Parity);
|
||||
} else if sr.fe() {
|
||||
r.rdr().read();
|
||||
return Err(Error::Framing);
|
||||
} else if sr.nf() {
|
||||
r.rdr().read();
|
||||
return Err(Error::Noise);
|
||||
} else if sr.ore() {
|
||||
r.rdr().read();
|
||||
return Err(Error::Overrun);
|
||||
} else if sr.rxne() {
|
||||
break;
|
||||
}
|
||||
}
|
||||
*b = r.rdr().read().0 as u8;
|
||||
}
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance, RxDma> embedded_hal::blocking::serial::Write<u8>
|
||||
for Uart<'d, T, NoDma, RxDma>
|
||||
{
|
||||
type Error = Error;
|
||||
fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
|
||||
unsafe {
|
||||
let r = self.inner.regs();
|
||||
for &b in buffer {
|
||||
while !r.isr().read().txe() {}
|
||||
r.tdr().write_value(regs::Dr(b as u32))
|
||||
}
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
fn bflush(&mut self) -> Result<(), Self::Error> {
|
||||
unsafe {
|
||||
let r = self.inner.regs();
|
||||
while !r.isr().read().tc() {}
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
// rustfmt::skip because intellij removes the 'where' claus on the associated type.
|
||||
impl<'d, T: Instance, TxDma, RxDma> embassy_traits::uart::Write for Uart<'d, T, TxDma, RxDma>
|
||||
where
|
||||
TxDma: crate::usart::TxDma<T>,
|
||||
{
|
||||
// rustfmt::skip because rustfmt removes the 'where' claus on the associated type.
|
||||
#[rustfmt::skip]
|
||||
type WriteFuture<'a> where Self: 'a = impl Future<Output = Result<(), embassy_traits::uart::Error>> +'a;
|
||||
|
||||
fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
|
||||
self.write_dma(buf)
|
||||
.map_err(|_| embassy_traits::uart::Error::Other)
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance, TxDma, RxDma> embassy_traits::uart::Read for Uart<'d, T, TxDma, RxDma>
|
||||
where
|
||||
RxDma: crate::usart::RxDma<T>,
|
||||
{
|
||||
// rustfmt::skip because rustfmt removes the 'where' claus on the associated type.
|
||||
#[rustfmt::skip]
|
||||
type ReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), embassy_traits::uart::Error>> + 'a;
|
||||
|
||||
fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
|
||||
self.read_dma(buf)
|
||||
.map_err(|_| embassy_traits::uart::Error::Other)
|
||||
}
|
||||
}
|
||||
|
||||
pub struct State<'d, T: Instance>(StateStorage<StateInner<'d, T>>);
|
||||
impl<'d, T: Instance> State<'d, T> {
|
||||
pub fn new() -> Self {
|
||||
Self(StateStorage::new())
|
||||
}
|
||||
}
|
||||
|
||||
pub struct StateInner<'d, T: Instance> {
|
||||
uart: Uart<'d, T, NoDma, NoDma>,
|
||||
phantom: PhantomData<&'d mut T>,
|
||||
|
||||
rx_waker: WakerRegistration,
|
||||
rx: RingBuffer<'d>,
|
||||
|
||||
tx_waker: WakerRegistration,
|
||||
tx: RingBuffer<'d>,
|
||||
}
|
||||
|
||||
unsafe impl<'d, T: Instance> Send for StateInner<'d, T> {}
|
||||
unsafe impl<'d, T: Instance> Sync for StateInner<'d, T> {}
|
||||
|
||||
pub struct BufferedUart<'d, T: Instance> {
|
||||
inner: PeripheralMutex<'d, StateInner<'d, T>>,
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> Unpin for BufferedUart<'d, T> {}
|
||||
|
||||
impl<'d, T: Instance> BufferedUart<'d, T> {
|
||||
pub unsafe fn new(
|
||||
state: &'d mut State<'d, T>,
|
||||
uart: Uart<'d, T, NoDma, NoDma>,
|
||||
irq: impl Unborrow<Target = T::Interrupt> + 'd,
|
||||
tx_buffer: &'d mut [u8],
|
||||
rx_buffer: &'d mut [u8],
|
||||
) -> BufferedUart<'d, T> {
|
||||
unborrow!(irq);
|
||||
|
||||
let r = uart.inner.regs();
|
||||
r.cr1().modify(|w| {
|
||||
w.set_rxneie(true);
|
||||
w.set_idleie(true);
|
||||
});
|
||||
|
||||
Self {
|
||||
inner: PeripheralMutex::new_unchecked(irq, &mut state.0, move || StateInner {
|
||||
uart,
|
||||
phantom: PhantomData,
|
||||
tx: RingBuffer::new(tx_buffer),
|
||||
tx_waker: WakerRegistration::new(),
|
||||
|
||||
rx: RingBuffer::new(rx_buffer),
|
||||
rx_waker: WakerRegistration::new(),
|
||||
}),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> StateInner<'d, T>
|
||||
where
|
||||
Self: 'd,
|
||||
{
|
||||
fn on_rx(&mut self) {
|
||||
let r = self.uart.inner.regs();
|
||||
unsafe {
|
||||
let sr = r.isr().read();
|
||||
if sr.pe() {
|
||||
r.icr().write(|w| {
|
||||
w.set_pe(true);
|
||||
});
|
||||
trace!("Parity error");
|
||||
} else if sr.fe() {
|
||||
r.icr().write(|w| {
|
||||
w.set_fe(true);
|
||||
});
|
||||
trace!("Framing error");
|
||||
} else if sr.nf() {
|
||||
r.icr().write(|w| {
|
||||
w.set_nf(true);
|
||||
});
|
||||
trace!("Noise error");
|
||||
} else if sr.ore() {
|
||||
r.icr().write(|w| {
|
||||
w.set_ore(true);
|
||||
});
|
||||
trace!("Overrun error");
|
||||
} else if sr.rxne() {
|
||||
let buf = self.rx.push_buf();
|
||||
if buf.is_empty() {
|
||||
self.rx_waker.wake();
|
||||
} else {
|
||||
buf[0] = r.rdr().read().0 as u8;
|
||||
self.rx.push(1);
|
||||
}
|
||||
} else if sr.idle() {
|
||||
r.icr().write(|w| {
|
||||
w.set_idle(true);
|
||||
});
|
||||
self.rx_waker.wake();
|
||||
};
|
||||
}
|
||||
}
|
||||
|
||||
fn on_tx(&mut self) {
|
||||
let r = self.uart.inner.regs();
|
||||
unsafe {
|
||||
if r.isr().read().txe() {
|
||||
let buf = self.tx.pop_buf();
|
||||
if !buf.is_empty() {
|
||||
r.cr1().modify(|w| {
|
||||
w.set_txeie(true);
|
||||
});
|
||||
r.tdr().write_value(regs::Dr(buf[0].into()));
|
||||
self.tx.pop(1);
|
||||
self.tx_waker.wake();
|
||||
} else {
|
||||
// Disable interrupt until we have something to transmit again
|
||||
r.cr1().modify(|w| {
|
||||
w.set_txeie(false);
|
||||
});
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> PeripheralState for StateInner<'d, T>
|
||||
where
|
||||
Self: 'd,
|
||||
{
|
||||
type Interrupt = T::Interrupt;
|
||||
fn on_interrupt(&mut self) {
|
||||
self.on_rx();
|
||||
self.on_tx();
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> embassy::io::AsyncBufRead for BufferedUart<'d, T> {
|
||||
fn poll_fill_buf(
|
||||
mut self: Pin<&mut Self>,
|
||||
cx: &mut Context<'_>,
|
||||
) -> Poll<Result<&[u8], embassy::io::Error>> {
|
||||
self.inner.with(|state| {
|
||||
compiler_fence(Ordering::SeqCst);
|
||||
|
||||
// We have data ready in buffer? Return it.
|
||||
let buf = state.rx.pop_buf();
|
||||
if !buf.is_empty() {
|
||||
let buf: &[u8] = buf;
|
||||
// Safety: buffer lives as long as uart
|
||||
let buf: &[u8] = unsafe { core::mem::transmute(buf) };
|
||||
return Poll::Ready(Ok(buf));
|
||||
}
|
||||
|
||||
state.rx_waker.register(cx.waker());
|
||||
Poll::<Result<&[u8], embassy::io::Error>>::Pending
|
||||
})
|
||||
}
|
||||
fn consume(mut self: Pin<&mut Self>, amt: usize) {
|
||||
let signal = self.inner.with(|state| {
|
||||
let full = state.rx.is_full();
|
||||
state.rx.pop(amt);
|
||||
full
|
||||
});
|
||||
if signal {
|
||||
self.inner.pend();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> embassy::io::AsyncWrite for BufferedUart<'d, T> {
|
||||
fn poll_write(
|
||||
mut self: Pin<&mut Self>,
|
||||
cx: &mut Context<'_>,
|
||||
buf: &[u8],
|
||||
) -> Poll<Result<usize, embassy::io::Error>> {
|
||||
let (poll, empty) = self.inner.with(|state| {
|
||||
let empty = state.tx.is_empty();
|
||||
let tx_buf = state.tx.push_buf();
|
||||
if tx_buf.is_empty() {
|
||||
state.tx_waker.register(cx.waker());
|
||||
return (Poll::Pending, empty);
|
||||
}
|
||||
|
||||
let n = core::cmp::min(tx_buf.len(), buf.len());
|
||||
tx_buf[..n].copy_from_slice(&buf[..n]);
|
||||
state.tx.push(n);
|
||||
|
||||
(Poll::Ready(Ok(n)), empty)
|
||||
});
|
||||
if empty {
|
||||
self.inner.pend();
|
||||
}
|
||||
poll
|
||||
}
|
||||
}
|
||||
@ -1 +1 @@
|
||||
Subproject commit 3e883bdff7fbb1f96be353d2c062be57ec8921a3
|
||||
Subproject commit 5506d27471c7e3297450127c3279f3dab96c94f8
|
||||
Loading…
Reference in New Issue
Block a user