Checkpoint.
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386e4bf0de
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@ -1,5 +1,8 @@
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[target.'cfg(all(target_arch = "arm", target_os = "none"))']
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[target.'cfg(all(target_arch = "arm", target_os = "none"))']
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runner = "probe-run --chip STM32F401CCUx"
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#runner = "probe-run --chip STM32F401CCUx"
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#runner = "probe-run --chip STM32L4S5VITx"
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#runner = "probe-run --chip ${PROBE_RUN_CHIP}"
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runner = "probe-run"
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rustflags = [
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rustflags = [
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# LLD (shipped with the Rust toolchain) is used as the default linker
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# LLD (shipped with the Rust toolchain) is used as the default linker
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@ -25,4 +28,5 @@ rustflags = [
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]
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]
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[build]
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[build]
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target = "thumbv7em-none-eabihf"
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#target = "thumbv7em-none-eabihf"
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target = "thumbv7em-none-eabi"
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@ -18,9 +18,11 @@ defmt-error = []
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[dependencies]
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[dependencies]
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embassy = { version = "0.1.0", path = "../embassy", features = ["defmt", "defmt-trace"] }
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embassy = { version = "0.1.0", path = "../embassy", features = ["defmt", "defmt-trace"] }
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embassy-traits = { version = "0.1.0", path = "../embassy-traits", features = ["defmt"] }
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embassy-traits = { version = "0.1.0", path = "../embassy-traits", features = ["defmt"] }
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embassy-stm32 = { version = "0.1.0", path = "../embassy-stm32", features = ["defmt", "defmt-trace", "stm32f429zi"] }
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#embassy-stm32 = { version = "0.1.0", path = "../embassy-stm32", features = ["defmt", "defmt-trace", "stm32f429zi"] }
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embassy-stm32 = { version = "0.1.0", path = "../embassy-stm32", features = ["defmt", "defmt-trace", "stm32l4s5vi"] }
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embassy-extras = {version = "0.1.0", path = "../embassy-extras" }
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embassy-extras = {version = "0.1.0", path = "../embassy-extras" }
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stm32f4 = { version = "0.13", features = ["stm32f429"] }
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#stm32f4 = { version = "0.13", features = ["stm32f429"] }
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stm32l4 = { version = "0.13", features = ["stm32l4x5" ] }
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defmt = "0.2.0"
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defmt = "0.2.0"
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defmt-rtt = "0.2.0"
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defmt-rtt = "0.2.0"
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@ -12,7 +12,8 @@ use embedded_hal::digital::v2::OutputPin;
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use example_common::*;
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use example_common::*;
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use cortex_m_rt::entry;
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use cortex_m_rt::entry;
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use stm32f4::stm32f429 as pac;
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//use stm32f4::stm32f429 as pac;
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use stm32l4::stm32l4x5 as pac;
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#[entry]
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#[entry]
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fn main() -> ! {
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fn main() -> ! {
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@ -25,21 +26,21 @@ fn main() -> ! {
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w.dbg_standby().set_bit();
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w.dbg_standby().set_bit();
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w.dbg_stop().set_bit()
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w.dbg_stop().set_bit()
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});
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});
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pp.RCC.ahb1enr.modify(|_, w| w.dma1en().enabled());
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pp.RCC.ahb1enr.modify(|_, w| w.dma1en().set_bit());
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pp.RCC.ahb1enr.modify(|_, w| {
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pp.RCC.ahb2enr.modify(|_, w| {
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w.gpioaen().enabled();
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w.gpioaen().set_bit();
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w.gpioben().enabled();
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w.gpioben().set_bit();
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w.gpiocen().enabled();
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w.gpiocen().set_bit();
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w.gpioden().enabled();
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w.gpioden().set_bit();
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w.gpioeen().enabled();
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w.gpioeen().set_bit();
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w.gpiofen().enabled();
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w.gpiofen().set_bit();
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w
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w
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});
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});
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let p = embassy_stm32::init(Default::default());
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let p = embassy_stm32::init(Default::default());
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let mut led = Output::new(p.PB7, Level::High);
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let mut led = Output::new(p.PA5, Level::High);
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loop {
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loop {
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info!("high");
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info!("high");
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@ -16,7 +16,8 @@ use embassy_traits::gpio::{WaitForFallingEdge, WaitForRisingEdge};
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use example_common::*;
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use example_common::*;
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use cortex_m_rt::entry;
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use cortex_m_rt::entry;
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use stm32f4::stm32f429 as pac;
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//use stm32f4::stm32f429 as pac;
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use stm32l4::stm32l4x5 as pac;
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#[embassy::task]
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#[embassy::task]
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async fn main_task() {
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async fn main_task() {
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@ -56,19 +57,20 @@ fn main() -> ! {
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w.dbg_standby().set_bit();
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w.dbg_standby().set_bit();
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w.dbg_stop().set_bit()
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w.dbg_stop().set_bit()
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});
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});
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pp.RCC.ahb1enr.modify(|_, w| w.dma1en().enabled());
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pp.RCC.ahb1enr.modify(|_, w| {
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pp.RCC.ahb1enr.modify(|_, w| w.dma1en().set_bit());
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w.gpioaen().enabled();
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w.gpioben().enabled();
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pp.RCC.ahb2enr.modify(|_, w| {
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w.gpiocen().enabled();
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w.gpioaen().set_bit();
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w.gpioden().enabled();
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w.gpioben().set_bit();
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w.gpioeen().enabled();
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w.gpiocen().set_bit();
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w.gpiofen().enabled();
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w.gpioden().set_bit();
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w.gpioeen().set_bit();
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w.gpiofen().set_bit();
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w
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w
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});
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});
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pp.RCC.apb2enr.modify(|_, w| {
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pp.RCC.apb2enr.modify(|_, w| {
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w.syscfgen().enabled();
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w.syscfgen().set_bit();
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w
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w
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});
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});
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