diff --git a/ci.sh b/ci.sh
index 82b72ae3..47bf5d66 100755
--- a/ci.sh
+++ b/ci.sh
@@ -119,6 +119,7 @@ cargo batch  \
     --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32g071rb --out-dir out/tests/nucleo-stm32g071rb \
     --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h755zi --out-dir out/tests/nucleo-stm32h755zi \
     --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wb55rg --out-dir out/tests/nucleo-stm32wb55rg \
+    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h563zi --out-dir out/tests/nucleo-stm32h563zi \
     --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32u585ai --out-dir out/tests/iot-stm32u585ai \
     --- build --release --manifest-path tests/rp/Cargo.toml --target thumbv6m-none-eabi --out-dir out/tests/rpi-pico \
     --- build --release --manifest-path tests/nrf/Cargo.toml --target thumbv7em-none-eabi --out-dir out/tests/nrf52840-dk \
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 4ab30622..a8ebacd2 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -58,7 +58,7 @@ sdio-host = "0.5.0"
 embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "46d1b1c2ff13e31e282ec1e352421721694f126a", optional = true }
 critical-section = "1.1"
 atomic-polyfill = "1.0.1"
-stm32-metapac = "4"
+stm32-metapac = "5"
 vcell = "0.1.3"
 bxcan = "0.7.0"
 nb = "1.0.0"
@@ -73,7 +73,7 @@ critical-section = { version = "1.1", features = ["std"] }
 [build-dependencies]
 proc-macro2 = "1.0.36"
 quote = "1.0.15"
-stm32-metapac = { version = "4", default-features = false, features = ["metadata"]}
+stm32-metapac = { version = "5", default-features = false, features = ["metadata"]}
 
 [features]
 default = ["stm32-metapac/rt"]
diff --git a/embassy-stm32/src/dma/gpdma.rs b/embassy-stm32/src/dma/gpdma.rs
index 442fee48..6f26fd19 100644
--- a/embassy-stm32/src/dma/gpdma.rs
+++ b/embassy-stm32/src/dma/gpdma.rs
@@ -190,6 +190,10 @@ mod low_level_api {
         fence(Ordering::SeqCst);
 
         let ch = dma.ch(channel_number as _);
+
+        // Reset ch
+        ch.cr().write(|w| w.set_reset(true));
+
         ch.llr().write(|_| {}); // no linked list
         ch.tr1().write(|w| {
             w.set_sdw(data_size.into());
@@ -252,7 +256,7 @@ mod low_level_api {
     /// Gets the running status of the channel
     pub unsafe fn is_running(dma: Gpdma, ch: u8) -> bool {
         let ch = dma.ch(ch as _);
-        !ch.sr().read().idlef()
+        !ch.sr().read().tcf()
     }
 
     /// Gets the total remaining transfers for the channel
@@ -291,7 +295,10 @@ mod low_level_api {
         }
 
         if sr.suspf() || sr.tcf() {
-            ch.cr().write(|w| w.set_reset(true));
+            // disable all xxIEs to prevent the irq from firing again.
+            ch.cr().write(|_| {});
+
+            // Wake the future. It'll look at tcf and see it's set.
             STATE.channels[state_index].waker.wake();
         }
     }
diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index 1f170887..481ea4ab 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -258,7 +258,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
                 w.set_spe(true);
             });
         }
-        #[cfg(any(spi_v3, spi_v4))]
+        #[cfg(any(spi_v3, spi_v4, spi_v5))]
         unsafe {
             T::REGS.ifcr().write(|w| w.0 = 0xffff_ffff);
             T::REGS.cfg2().modify(|w| {
@@ -317,7 +317,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
             });
         }
 
-        #[cfg(any(spi_v3, spi_v4))]
+        #[cfg(any(spi_v3, spi_v4, spi_v5))]
         unsafe {
             T::REGS.cfg2().modify(|w| {
                 w.set_cpha(cpha);
@@ -330,7 +330,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
     pub fn get_current_config(&self) -> Config {
         #[cfg(any(spi_v1, spi_f1, spi_v2))]
         let cfg = unsafe { T::REGS.cr1().read() };
-        #[cfg(any(spi_v3, spi_v4))]
+        #[cfg(any(spi_v3, spi_v4, spi_v5))]
         let cfg = unsafe { T::REGS.cfg2().read() };
         let polarity = if cfg.cpol() == vals::Cpol::IDLELOW {
             Polarity::IdleLow
@@ -383,7 +383,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
                 w.set_spe(true);
             });
         }
-        #[cfg(any(spi_v3, spi_v4))]
+        #[cfg(any(spi_v3, spi_v4, spi_v5))]
         unsafe {
             T::REGS.cr1().modify(|w| {
                 w.set_csusp(true);
@@ -429,7 +429,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
             T::REGS.cr1().modify(|w| {
                 w.set_spe(true);
             });
-            #[cfg(any(spi_v3, spi_v4))]
+            #[cfg(any(spi_v3, spi_v4, spi_v5))]
             T::REGS.cr1().modify(|w| {
                 w.set_cstart(true);
             });
@@ -459,7 +459,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
         }
 
         // SPIv3 clears rxfifo on SPE=0
-        #[cfg(not(any(spi_v3, spi_v4)))]
+        #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
         flush_rx_fifo(T::REGS);
 
         set_rxdmaen(T::REGS, true);
@@ -481,7 +481,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
             T::REGS.cr1().modify(|w| {
                 w.set_spe(true);
             });
-            #[cfg(any(spi_v3, spi_v4))]
+            #[cfg(any(spi_v3, spi_v4, spi_v5))]
             T::REGS.cr1().modify(|w| {
                 w.set_cstart(true);
             });
@@ -514,7 +514,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
         }
 
         // SPIv3 clears rxfifo on SPE=0
-        #[cfg(not(any(spi_v3, spi_v4)))]
+        #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
         flush_rx_fifo(T::REGS);
 
         set_rxdmaen(T::REGS, true);
@@ -534,7 +534,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
             T::REGS.cr1().modify(|w| {
                 w.set_spe(true);
             });
-            #[cfg(any(spi_v3, spi_v4))]
+            #[cfg(any(spi_v3, spi_v4, spi_v5))]
             T::REGS.cr1().modify(|w| {
                 w.set_cstart(true);
             });
@@ -619,9 +619,9 @@ impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> {
     }
 }
 
-#[cfg(not(any(spi_v3, spi_v4)))]
+#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
 use vals::Br;
-#[cfg(any(spi_v3, spi_v4))]
+#[cfg(any(spi_v3, spi_v4, spi_v5))]
 use vals::Mbr as Br;
 
 fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> Br {
@@ -647,17 +647,17 @@ trait RegsExt {
 
 impl RegsExt for Regs {
     fn tx_ptr<W>(&self) -> *mut W {
-        #[cfg(not(any(spi_v3, spi_v4)))]
+        #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
         let dr = self.dr();
-        #[cfg(any(spi_v3, spi_v4))]
+        #[cfg(any(spi_v3, spi_v4, spi_v5))]
         let dr = self.txdr();
         dr.ptr() as *mut W
     }
 
     fn rx_ptr<W>(&self) -> *mut W {
-        #[cfg(not(any(spi_v3, spi_v4)))]
+        #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
         let dr = self.dr();
-        #[cfg(any(spi_v3, spi_v4))]
+        #[cfg(any(spi_v3, spi_v4, spi_v5))]
         let dr = self.rxdr();
         dr.ptr() as *mut W
     }
@@ -667,22 +667,22 @@ fn check_error_flags(sr: regs::Sr) -> Result<(), Error> {
     if sr.ovr() {
         return Err(Error::Overrun);
     }
-    #[cfg(not(any(spi_f1, spi_v3, spi_v4)))]
+    #[cfg(not(any(spi_f1, spi_v3, spi_v4, spi_v5)))]
     if sr.fre() {
         return Err(Error::Framing);
     }
-    #[cfg(any(spi_v3, spi_v4))]
+    #[cfg(any(spi_v3, spi_v4, spi_v5))]
     if sr.tifre() {
         return Err(Error::Framing);
     }
     if sr.modf() {
         return Err(Error::ModeFault);
     }
-    #[cfg(not(any(spi_v3, spi_v4)))]
+    #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
     if sr.crcerr() {
         return Err(Error::Crc);
     }
-    #[cfg(any(spi_v3, spi_v4))]
+    #[cfg(any(spi_v3, spi_v4, spi_v5))]
     if sr.crce() {
         return Err(Error::Crc);
     }
@@ -696,11 +696,11 @@ fn spin_until_tx_ready(regs: Regs) -> Result<(), Error> {
 
         check_error_flags(sr)?;
 
-        #[cfg(not(any(spi_v3, spi_v4)))]
+        #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
         if sr.txe() {
             return Ok(());
         }
-        #[cfg(any(spi_v3, spi_v4))]
+        #[cfg(any(spi_v3, spi_v4, spi_v5))]
         if sr.txp() {
             return Ok(());
         }
@@ -713,11 +713,11 @@ fn spin_until_rx_ready(regs: Regs) -> Result<(), Error> {
 
         check_error_flags(sr)?;
 
-        #[cfg(not(any(spi_v3, spi_v4)))]
+        #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
         if sr.rxne() {
             return Ok(());
         }
-        #[cfg(any(spi_v3, spi_v4))]
+        #[cfg(any(spi_v3, spi_v4, spi_v5))]
         if sr.rxp() {
             return Ok(());
         }
@@ -726,11 +726,11 @@ fn spin_until_rx_ready(regs: Regs) -> Result<(), Error> {
 
 fn flush_rx_fifo(regs: Regs) {
     unsafe {
-        #[cfg(not(any(spi_v3, spi_v4)))]
+        #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
         while regs.sr().read().rxne() {
             let _ = regs.dr().read();
         }
-        #[cfg(any(spi_v3, spi_v4))]
+        #[cfg(any(spi_v3, spi_v4, spi_v5))]
         while regs.sr().read().rxp() {
             let _ = regs.rxdr().read();
         }
@@ -739,11 +739,11 @@ fn flush_rx_fifo(regs: Regs) {
 
 fn set_txdmaen(regs: Regs, val: bool) {
     unsafe {
-        #[cfg(not(any(spi_v3, spi_v4)))]
+        #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
         regs.cr2().modify(|reg| {
             reg.set_txdmaen(val);
         });
-        #[cfg(any(spi_v3, spi_v4))]
+        #[cfg(any(spi_v3, spi_v4, spi_v5))]
         regs.cfg1().modify(|reg| {
             reg.set_txdmaen(val);
         });
@@ -752,11 +752,11 @@ fn set_txdmaen(regs: Regs, val: bool) {
 
 fn set_rxdmaen(regs: Regs, val: bool) {
     unsafe {
-        #[cfg(not(any(spi_v3, spi_v4)))]
+        #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
         regs.cr2().modify(|reg| {
             reg.set_rxdmaen(val);
         });
-        #[cfg(any(spi_v3, spi_v4))]
+        #[cfg(any(spi_v3, spi_v4, spi_v5))]
         regs.cfg1().modify(|reg| {
             reg.set_rxdmaen(val);
         });
@@ -768,9 +768,9 @@ fn finish_dma(regs: Regs) {
         #[cfg(spi_v2)]
         while regs.sr().read().ftlvl() > 0 {}
 
-        #[cfg(any(spi_v3, spi_v4))]
+        #[cfg(any(spi_v3, spi_v4, spi_v5))]
         while !regs.sr().read().txc() {}
-        #[cfg(not(any(spi_v3, spi_v4)))]
+        #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
         while regs.sr().read().bsy() {}
 
         // Disable the spi peripheral
@@ -780,12 +780,12 @@ fn finish_dma(regs: Regs) {
 
         // The peripheral automatically disables the DMA stream on completion without error,
         // but it does not clear the RXDMAEN/TXDMAEN flag in CR2.
-        #[cfg(not(any(spi_v3, spi_v4)))]
+        #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
         regs.cr2().modify(|reg| {
             reg.set_txdmaen(false);
             reg.set_rxdmaen(false);
         });
-        #[cfg(any(spi_v3, spi_v4))]
+        #[cfg(any(spi_v3, spi_v4, spi_v5))]
         regs.cfg1().modify(|reg| {
             reg.set_txdmaen(false);
             reg.set_rxdmaen(false);
@@ -799,7 +799,7 @@ fn transfer_word<W: Word>(regs: Regs, tx_word: W) -> Result<W, Error> {
     unsafe {
         ptr::write_volatile(regs.tx_ptr(), tx_word);
 
-        #[cfg(any(spi_v3, spi_v4))]
+        #[cfg(any(spi_v3, spi_v4, spi_v5))]
         regs.cr1().modify(|reg| reg.set_cstart(true));
     }
 
@@ -970,7 +970,7 @@ pub(crate) mod sealed {
             }
         }
 
-        #[cfg(any(spi_v3, spi_v4))]
+        #[cfg(any(spi_v3, spi_v4, spi_v5))]
         pub fn dsize(&self) -> u8 {
             match self {
                 WordSize::EightBit => 0b0111,
@@ -978,7 +978,7 @@ pub(crate) mod sealed {
             }
         }
 
-        #[cfg(any(spi_v3, spi_v4))]
+        #[cfg(any(spi_v3, spi_v4, spi_v5))]
         pub fn _frxth(&self) -> vals::Fthlv {
             match self {
                 WordSize::EightBit => vals::Fthlv::ONEFRAME,
diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml
index 6070a5a8..bd181f23 100644
--- a/tests/stm32/Cargo.toml
+++ b/tests/stm32/Cargo.toml
@@ -11,6 +11,7 @@ stm32g071rb = ["embassy-stm32/stm32g071rb"]     # Nucleo
 stm32g491re = ["embassy-stm32/stm32g491re"]     # Nucleo
 stm32h755zi = ["embassy-stm32/stm32h755zi-cm7"] # Nucleo
 stm32wb55rg = ["embassy-stm32/stm32wb55rg"]     # Nucleo
+stm32h563zi = ["embassy-stm32/stm32h563zi"]     # Nucleo
 stm32u585ai = ["embassy-stm32/stm32u585ai"]     # IoT board
 
 [dependencies]
diff --git a/tests/stm32/src/bin/gpio.rs b/tests/stm32/src/bin/gpio.rs
index 18fd85d4..6a36df8c 100644
--- a/tests/stm32/src/bin/gpio.rs
+++ b/tests/stm32/src/bin/gpio.rs
@@ -30,6 +30,8 @@ async fn main(_spawner: Spawner) {
     let (mut a, mut b) = (p.PB6, p.PB7);
     #[cfg(feature = "stm32u585ai")]
     let (mut a, mut b) = (p.PD9, p.PD8);
+    #[cfg(feature = "stm32h563zi")]
+    let (mut a, mut b) = (p.PB6, p.PB7);
 
     // Test initial output
     {
diff --git a/tests/stm32/src/bin/spi.rs b/tests/stm32/src/bin/spi.rs
index 1c5dc87c..bf8098b1 100644
--- a/tests/stm32/src/bin/spi.rs
+++ b/tests/stm32/src/bin/spi.rs
@@ -17,22 +17,25 @@ async fn main(_spawner: Spawner) {
     info!("Hello World!");
 
     #[cfg(feature = "stm32f103c8")]
-    let (sck, mosi, miso) = (p.PA5, p.PA7, p.PA6);
+    let (spi, sck, mosi, miso) = (p.SPI1, p.PA5, p.PA7, p.PA6);
     #[cfg(feature = "stm32f429zi")]
-    let (sck, mosi, miso) = (p.PA5, p.PA7, p.PA6);
+    let (spi, sck, mosi, miso) = (p.SPI1, p.PA5, p.PA7, p.PA6);
     #[cfg(feature = "stm32h755zi")]
-    let (sck, mosi, miso) = (p.PA5, p.PB5, p.PA6);
+    let (spi, sck, mosi, miso) = (p.SPI1, p.PA5, p.PB5, p.PA6);
     #[cfg(feature = "stm32g491re")]
-    let (sck, mosi, miso) = (p.PA5, p.PA7, p.PA6);
+    let (spi, sck, mosi, miso) = (p.SPI1, p.PA5, p.PA7, p.PA6);
     #[cfg(feature = "stm32g071rb")]
-    let (sck, mosi, miso) = (p.PA5, p.PA7, p.PA6);
+    let (spi, sck, mosi, miso) = (p.SPI1, p.PA5, p.PA7, p.PA6);
     #[cfg(feature = "stm32wb55rg")]
-    let (sck, mosi, miso) = (p.PA5, p.PA7, p.PA6);
+    let (spi, sck, mosi, miso) = (p.SPI1, p.PA5, p.PA7, p.PA6);
     #[cfg(feature = "stm32u585ai")]
-    let (sck, mosi, miso) = (p.PE13, p.PE15, p.PE14);
+    let (spi, sck, mosi, miso) = (p.SPI1, p.PE13, p.PE15, p.PE14);
+    #[cfg(feature = "stm32h563zi")]
+    let (spi, sck, mosi, miso) = (p.SPI4, p.PE12, p.PE14, p.PE13);
 
+    info!("asdfa;");
     let mut spi = Spi::new(
-        p.SPI1,
+        spi,
         sck,  // Arduino D13
         mosi, // Arduino D11
         miso, // Arduino D12
diff --git a/tests/stm32/src/bin/spi_dma.rs b/tests/stm32/src/bin/spi_dma.rs
index cb2152e0..b3dad813 100644
--- a/tests/stm32/src/bin/spi_dma.rs
+++ b/tests/stm32/src/bin/spi_dma.rs
@@ -16,22 +16,24 @@ async fn main(_spawner: Spawner) {
     info!("Hello World!");
 
     #[cfg(feature = "stm32f103c8")]
-    let (sck, mosi, miso, tx_dma, rx_dma) = (p.PA5, p.PA7, p.PA6, p.DMA1_CH3, p.DMA1_CH2);
+    let (spi, sck, mosi, miso, tx_dma, rx_dma) = (p.SPI1, p.PA5, p.PA7, p.PA6, p.DMA1_CH3, p.DMA1_CH2);
     #[cfg(feature = "stm32f429zi")]
-    let (sck, mosi, miso, tx_dma, rx_dma) = (p.PA5, p.PA7, p.PA6, p.DMA2_CH3, p.DMA2_CH2);
+    let (spi, sck, mosi, miso, tx_dma, rx_dma) = (p.SPI1, p.PA5, p.PA7, p.PA6, p.DMA2_CH3, p.DMA2_CH2);
     #[cfg(feature = "stm32h755zi")]
-    let (sck, mosi, miso, tx_dma, rx_dma) = (p.PA5, p.PB5, p.PA6, p.DMA1_CH0, p.DMA1_CH1);
+    let (spi, sck, mosi, miso, tx_dma, rx_dma) = (p.SPI1, p.PA5, p.PB5, p.PA6, p.DMA1_CH0, p.DMA1_CH1);
     #[cfg(feature = "stm32g491re")]
-    let (sck, mosi, miso, tx_dma, rx_dma) = (p.PA5, p.PA7, p.PA6, p.DMA1_CH1, p.DMA1_CH2);
+    let (spi, sck, mosi, miso, tx_dma, rx_dma) = (p.SPI1, p.PA5, p.PA7, p.PA6, p.DMA1_CH1, p.DMA1_CH2);
     #[cfg(feature = "stm32g071rb")]
-    let (sck, mosi, miso, tx_dma, rx_dma) = (p.PA5, p.PA7, p.PA6, p.DMA1_CH1, p.DMA1_CH2);
+    let (spi, sck, mosi, miso, tx_dma, rx_dma) = (p.SPI1, p.PA5, p.PA7, p.PA6, p.DMA1_CH1, p.DMA1_CH2);
     #[cfg(feature = "stm32wb55rg")]
-    let (sck, mosi, miso, tx_dma, rx_dma) = (p.PA5, p.PA7, p.PA6, p.DMA1_CH1, p.DMA1_CH2);
+    let (spi, sck, mosi, miso, tx_dma, rx_dma) = (p.SPI1, p.PA5, p.PA7, p.PA6, p.DMA1_CH1, p.DMA1_CH2);
     #[cfg(feature = "stm32u585ai")]
-    let (sck, mosi, miso, tx_dma, rx_dma) = (p.PE13, p.PE15, p.PE14, p.GPDMA1_CH0, p.GPDMA1_CH1);
+    let (spi, sck, mosi, miso, tx_dma, rx_dma) = (p.SPI1, p.PE13, p.PE15, p.PE14, p.GPDMA1_CH0, p.GPDMA1_CH1);
+    #[cfg(feature = "stm32h563zi")]
+    let (spi, sck, mosi, miso, tx_dma, rx_dma) = (p.SPI4, p.PE12, p.PE14, p.PE13, p.GPDMA1_CH0, p.GPDMA1_CH1);
 
     let mut spi = Spi::new(
-        p.SPI1,
+        spi,
         sck,  // Arduino D13
         mosi, // Arduino D11
         miso, // Arduino D12
diff --git a/tests/stm32/src/bin/usart.rs b/tests/stm32/src/bin/usart.rs
index af55867f..52409567 100644
--- a/tests/stm32/src/bin/usart.rs
+++ b/tests/stm32/src/bin/usart.rs
@@ -32,6 +32,8 @@ async fn main(_spawner: Spawner) {
     let (tx, rx, usart, irq) = (p.PB6, p.PB7, p.USART1, interrupt::take!(USART1));
     #[cfg(feature = "stm32u585ai")]
     let (tx, rx, usart, irq) = (p.PD8, p.PD9, p.USART3, interrupt::take!(USART3));
+    #[cfg(feature = "stm32h563zi")]
+    let (tx, rx, usart, irq) = (p.PB6, p.PB7, p.LPUART1, interrupt::take!(LPUART1));
 
     let config = Config::default();
     let mut usart = Uart::new(usart, rx, tx, irq, NoDma, NoDma, config);
diff --git a/tests/stm32/src/bin/usart_dma.rs b/tests/stm32/src/bin/usart_dma.rs
index d12605a9..3f70791c 100644
--- a/tests/stm32/src/bin/usart_dma.rs
+++ b/tests/stm32/src/bin/usart_dma.rs
@@ -62,6 +62,15 @@ async fn main(_spawner: Spawner) {
         p.GPDMA1_CH0,
         p.GPDMA1_CH1,
     );
+    #[cfg(feature = "stm32h563zi")]
+    let (tx, rx, usart, irq, tx_dma, rx_dma) = (
+        p.PB6,
+        p.PB7,
+        p.LPUART1,
+        interrupt::take!(LPUART1),
+        p.GPDMA1_CH0,
+        p.GPDMA1_CH1,
+    );
 
     let config = Config::default();
     let mut usart = Uart::new(usart, rx, tx, irq, tx_dma, rx_dma, config);