diff --git a/embassy-stm32/src/i2s.rs b/embassy-stm32/src/i2s.rs index 8fd3a8c6..67d40c47 100644 --- a/embassy-stm32/src/i2s.rs +++ b/embassy-stm32/src/i2s.rs @@ -170,7 +170,7 @@ impl<'d, T: Instance, Tx, Rx> I2S<'d, T, Tx, Rx> { let spi = Spi::new_internal(peri, txdma, rxdma, spi_cfg); #[cfg(all(rcc_f4, not(stm32f410)))] - let pclk = unsafe { get_freqs() }.plli2s.unwrap(); + let pclk = unsafe { get_freqs() }.plli2s1_q.unwrap(); #[cfg(stm32f410)] let pclk = T::frequency(); diff --git a/embassy-stm32/src/rcc/f2.rs b/embassy-stm32/src/rcc/f2.rs index ab588233..34720e83 100644 --- a/embassy-stm32/src/rcc/f2.rs +++ b/embassy-stm32/src/rcc/f2.rs @@ -314,7 +314,7 @@ pub(crate) unsafe fn init(config: Config) { apb1_tim: apb1_tim_freq, apb2: apb2_freq, apb2_tim: apb2_tim_freq, - pll48: Some(pll_clocks.pll48_freq), + pll1_q: Some(pll_clocks.pll48_freq), rtc, }); } diff --git a/embassy-stm32/src/rcc/f4.rs b/embassy-stm32/src/rcc/f4.rs index 79c2d2f6..91ad81b2 100644 --- a/embassy-stm32/src/rcc/f4.rs +++ b/embassy-stm32/src/rcc/f4.rs @@ -350,13 +350,17 @@ pub(crate) unsafe fn init(config: Config) { ahb2: Hertz(hclk), ahb3: Hertz(hclk), - pll48: plls.pll48clk.map(Hertz), + pll1_q: plls.pll48clk.map(Hertz), #[cfg(not(stm32f410))] - plli2s: plls.plli2sclk.map(Hertz), + plli2s1_q: plls.plli2sclk.map(Hertz), + #[cfg(not(stm32f410))] + plli2s1_r: None, #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))] - pllsai: plls.pllsaiclk.map(Hertz), + pllsai1_q: plls.pllsaiclk.map(Hertz), + #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))] + pllsai1_r: None, rtc, }); diff --git a/embassy-stm32/src/rcc/f7.rs b/embassy-stm32/src/rcc/f7.rs index 0a0a1cf2..f0e01149 100644 --- a/embassy-stm32/src/rcc/f7.rs +++ b/embassy-stm32/src/rcc/f7.rs @@ -269,7 +269,7 @@ pub(crate) unsafe fn init(config: Config) { ahb2: Hertz(hclk), ahb3: Hertz(hclk), - pll48: plls.pll48clk.map(Hertz), + pll1_q: plls.pll48clk.map(Hertz), rtc, }); diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs index 1603a2c3..0cc9e6a6 100644 --- a/embassy-stm32/src/rcc/mod.rs +++ b/embassy-stm32/src/rcc/mod.rs @@ -104,24 +104,25 @@ pub struct Clocks { #[cfg(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7rm0433, rcc_h7ab, rcc_wba))] pub ahb4: Hertz, - #[cfg(any(rcc_f2, rcc_f4, rcc_f410, rcc_f7))] - pub pll48: Option, - #[cfg(all(rcc_f4, not(stm32f410)))] - pub plli2s: Option, + pub plli2s1_q: Option, + #[cfg(all(rcc_f4, not(stm32f410)))] + pub plli2s1_r: Option, #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))] - pub pllsai: Option, + pub pllsai1_q: Option, + #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))] + pub pllsai1_r: Option, #[cfg(stm32g4)] pub pll1_p: Option, - #[cfg(any(stm32h5, stm32h7))] + #[cfg(any(stm32h5, stm32h7, rcc_f2, rcc_f4, rcc_f410, rcc_f7))] pub pll1_q: Option, #[cfg(any(stm32h5, stm32h7))] - pub pll2_q: Option, - #[cfg(any(stm32h5, stm32h7))] pub pll2_p: Option, #[cfg(any(stm32h5, stm32h7))] + pub pll2_q: Option, + #[cfg(any(stm32h5, stm32h7))] pub pll2_r: Option, #[cfg(any(stm32h5, stm32h7))] pub pll3_p: Option, diff --git a/embassy-stm32/src/sdmmc/mod.rs b/embassy-stm32/src/sdmmc/mod.rs index bc29fe54..11ff2464 100644 --- a/embassy-stm32/src/sdmmc/mod.rs +++ b/embassy-stm32/src/sdmmc/mod.rs @@ -1457,7 +1457,7 @@ cfg_if::cfg_if! { macro_rules! kernel_clk { ($inst:ident) => { critical_section::with(|_| unsafe { - crate::rcc::get_freqs().pll48 + crate::rcc::get_freqs().pll1_q }).expect("PLL48 is required for SDIO") } } @@ -1469,7 +1469,7 @@ cfg_if::cfg_if! { if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYSCLK { crate::rcc::get_freqs().sys } else { - crate::rcc::get_freqs().pll48.expect("PLL48 is required for SDMMC") + crate::rcc::get_freqs().pll1_q.expect("PLL48 is required for SDMMC") } }) }; @@ -1479,7 +1479,7 @@ cfg_if::cfg_if! { if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYSCLK { crate::rcc::get_freqs().sys } else { - crate::rcc::get_freqs().pll48.expect("PLL48 is required for SDMMC") + crate::rcc::get_freqs().pll1_q.expect("PLL48 is required for SDMMC") } }) };