max/embassy
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Refactor IWDG to use LSI frequency from RCC

Browse Source
This commit is contained in:
chemicstry
2022-07-10 20:59:36 +03:00
parent bd01e90bfa
commit 1fd5022e72
17 changed files with 117 additions and 73 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
embassy-stm32/src/rcc/wl.rs
View File

@ -8,9 +8,13 @@ use crate::time::U32Ext;
/// Only the basic setup using the HSE and HSI clocks are supported as of now.
/// HSI speed
pub const HSI_FREQ: u32 = 16_000_000;
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
pub const HSE32_FREQ: u32 = 32_000_000;
/// LSI speed
pub const LSI_FREQ: Hertz = Hertz(32_000);
/// HSE32 speed
pub const HSE32_FREQ: Hertz = Hertz(32_000_000);
/// System clock mux source
#[derive(Clone, Copy)]
@ -203,7 +207,7 @@ pub(crate) unsafe fn init(config: Config) {
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
(HSI_FREQ, 0x01, VoltageScale::Range2)
(HSI_FREQ.0, 0x01, VoltageScale::Range2)
}
ClockSrc::HSE32 => {
// Enable HSE32
@ -213,7 +217,7 @@ pub(crate) unsafe fn init(config: Config) {
});
while !RCC.cr().read().hserdy() {}
(HSE32_FREQ, 0x02, VoltageScale::Range1)
(HSE32_FREQ.0, 0x02, VoltageScale::Range1)
}
ClockSrc::MSI(range) => {
RCC.cr().write(|w| {