diff --git a/embassy-stm32/src/fmc/mod.rs b/embassy-stm32/src/fmc/mod.rs
index 856a4adc..0c546104 100644
--- a/embassy-stm32/src/fmc/mod.rs
+++ b/embassy-stm32/src/fmc/mod.rs
@@ -27,9 +27,13 @@ where
     }
 
     fn memory_controller_enable(&mut self) {
-        // The FMCEN bit of the FMC_BCR2..4 registers is don’t
-        // care. It is only enabled through the FMC_BCR1 register.
-        unsafe { T::regs().bcr1().modify(|r| r.set_fmcen(true)) };
+        // fmc v1 and v2 does not have the fmcen bit
+        // fsmc v1 and v2 does not have the fmcen bit
+        // This is a "not" because it is expected that all future versions have this bit
+        #[cfg(not(any(fmc_v1x3, fmc_v2x1, fsmc_v1x3, fsmc_v2x1)))]
+        unsafe {
+            T::regs().bcr1().modify(|r| r.set_fmcen(true))
+        };
     }
 
     fn source_clock_hz(&self) -> u32 {