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Pass rx pin to right init arg

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This commit is contained in:
Jacob Davis-Hansson 2023-04-18 17:44:19 +02:00
parent 81f10e136a
commit 21ea98810a
1 changed files with 23 additions and 7 deletions
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30
embassy-rp/src/uart/mod.rs
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@ -5,8 +5,8 @@ use embassy_hal_common::{into_ref, PeripheralRef};
use crate::dma::{AnyChannel, Channel}; use crate::dma::{AnyChannel, Channel};
use crate::gpio::sealed::Pin; use crate::gpio::sealed::Pin;
use crate::gpio::AnyPin; use crate::gpio::AnyPin;
use crate::{pac, peripherals, Peripheral};
use crate::pac::io::vals::{Inover, Outover}; use crate::pac::io::vals::{Inover, Outover};
use crate::{pac, peripherals, Peripheral};
#[cfg(feature = "nightly")] #[cfg(feature = "nightly")]
mod buffered; mod buffered;
@ -180,7 +180,7 @@ impl<'d, T: Instance> UartTx<'d, T, Async> {
} }
impl<'d, T: Instance, M: Mode> UartRx<'d, T, M> { impl<'d, T: Instance, M: Mode> UartRx<'d, T, M> {
/// Create a new DMA-enabled UART which can only send data /// Create a new DMA-enabled UART which can only recieve data
pub fn new( pub fn new(
_uart: impl Peripheral<P = T> + 'd, _uart: impl Peripheral<P = T> + 'd,
rx: impl Peripheral<P = impl RxPin<T>> + 'd, rx: impl Peripheral<P = impl RxPin<T>> + 'd,
@ -188,7 +188,7 @@ impl<'d, T: Instance, M: Mode> UartRx<'d, T, M> {
config: Config, config: Config,
) -> Self { ) -> Self {
into_ref!(rx, rx_dma); into_ref!(rx, rx_dma);
Uart::<T, M>::init(Some(rx.map_into()), None, None, None, config); Uart::<T, M>::init(None, Some(rx.map_into()), None, None, config);
Self::new_inner(Some(rx_dma.map_into())) Self::new_inner(Some(rx_dma.map_into()))
} }
@ -396,28 +396,44 @@ impl<'d, T: Instance + 'd, M: Mode> Uart<'d, T, M> {
if let Some(pin) = &tx { if let Some(pin) = &tx {
pin.io().ctrl().write(|w| { pin.io().ctrl().write(|w| {
w.set_funcsel(2); w.set_funcsel(2);
w.set_outover(if config.invert_tx { Outover::INVERT } else { Outover::NORMAL }); w.set_outover(if config.invert_tx {
Outover::INVERT
} else {
Outover::NORMAL
});
}); });
pin.pad_ctrl().write(|w| w.set_ie(true)); pin.pad_ctrl().write(|w| w.set_ie(true));
} }
if let Some(pin) = &rx { if let Some(pin) = &rx {
pin.io().ctrl().write(|w| { pin.io().ctrl().write(|w| {
w.set_funcsel(2); w.set_funcsel(2);
w.set_inover(if config.invert_rx { Inover::INVERT } else { Inover::NORMAL }); w.set_inover(if config.invert_rx {
Inover::INVERT
} else {
Inover::NORMAL
});
}); });
pin.pad_ctrl().write(|w| w.set_ie(true)); pin.pad_ctrl().write(|w| w.set_ie(true));
} }
if let Some(pin) = &cts { if let Some(pin) = &cts {
pin.io().ctrl().write(|w| { pin.io().ctrl().write(|w| {
w.set_funcsel(2); w.set_funcsel(2);
w.set_inover(if config.invert_cts { Inover::INVERT } else { Inover::NORMAL }); w.set_inover(if config.invert_cts {
Inover::INVERT
} else {
Inover::NORMAL
});
}); });
pin.pad_ctrl().write(|w| w.set_ie(true)); pin.pad_ctrl().write(|w| w.set_ie(true));
} }
if let Some(pin) = &rts { if let Some(pin) = &rts {
pin.io().ctrl().write(|w| { pin.io().ctrl().write(|w| {
w.set_funcsel(2); w.set_funcsel(2);
w.set_outover(if config.invert_rts { Outover::INVERT } else { Outover::NORMAL }); w.set_outover(if config.invert_rts {
Outover::INVERT
} else {
Outover::NORMAL
});
}); });
pin.pad_ctrl().write(|w| w.set_ie(true)); pin.pad_ctrl().write(|w| w.set_ie(true));
} }