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This commit is contained in:
Bob McWhirter 2021-05-20 14:19:43 -04:00
parent 8b36269d65
commit 222faccbab
3 changed files with 31 additions and 80 deletions
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30
embassy-stm32/src/spi/v1.rs
View File

@ -5,10 +5,10 @@ use crate::pac::spi;
use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize}; use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize};
use crate::time::Hertz; use crate::time::Hertz;
use core::marker::PhantomData; use core::marker::PhantomData;
use core::ptr;
use embassy::util::Unborrow; use embassy::util::Unborrow;
use embassy_extras::unborrow; use embassy_extras::unborrow;
pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
use core::ptr;
impl WordSize { impl WordSize {
fn dff(&self) -> spi::vals::Dff { fn dff(&self) -> spi::vals::Dff {
@ -153,10 +153,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T> {
} }
unsafe { unsafe {
let dr = regs.txdr().ptr() as *mut u8; let dr = regs.txdr().ptr() as *mut u8;
ptr::write_volatile( ptr::write_volatile(dr, *word);
dr,
*word,
);
} }
loop { loop {
let sr = unsafe { regs.sr().read() }; let sr = unsafe { regs.sr().read() };
@ -192,10 +189,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> {
} }
unsafe { unsafe {
let dr = regs.txdr().ptr() as *mut u8; let dr = regs.txdr().ptr() as *mut u8;
ptr::write_volatile( ptr::write_volatile(dr, *word);
dr,
*word,
);
} }
while unsafe { !regs.sr().read().rxne() } { while unsafe { !regs.sr().read().rxne() } {
@ -204,9 +198,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> {
unsafe { unsafe {
let dr = regs.dr().ptr() as *const u8; let dr = regs.dr().ptr() as *const u8;
*word = ptr::read_volatile( *word = ptr::read_volatile(dr);
dr
);
} }
let sr = unsafe { regs.sr().read() }; let sr = unsafe { regs.sr().read() };
@ -238,10 +230,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T> {
} }
unsafe { unsafe {
let dr = regs.txdr().ptr() as *mut u16; let dr = regs.txdr().ptr() as *mut u16;
ptr::write_volatile( ptr::write_volatile(dr, *word);
dr,
*word,
);
} }
loop { loop {
let sr = unsafe { regs.sr().read() }; let sr = unsafe { regs.sr().read() };
@ -277,19 +266,14 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T>
} }
unsafe { unsafe {
let dr = regs.txdr().ptr() as *mut u16; let dr = regs.txdr().ptr() as *mut u16;
ptr::write_volatile( ptr::write_volatile(dr, *word);
dr,
*word,
);
} }
while unsafe { !regs.sr().read().rxne() } { while unsafe { !regs.sr().read().rxne() } {
// spin waiting for inbound to shift in. // spin waiting for inbound to shift in.
} }
unsafe { unsafe {
let dr = regs.dr().ptr() as *const u16; let dr = regs.dr().ptr() as *const u16;
*word = ptr::read_volatile( *word = ptr::read_volatile(dr);
dr
);
} }
let sr = unsafe { regs.sr().read() }; let sr = unsafe { regs.sr().read() };

30
embassy-stm32/src/spi/v2.rs
View File

@ -7,10 +7,10 @@ use crate::pac::spi;
use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize}; use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize};
use crate::time::Hertz; use crate::time::Hertz;
use core::marker::PhantomData; use core::marker::PhantomData;
use core::ptr;
use embassy::util::Unborrow; use embassy::util::Unborrow;
use embassy_extras::unborrow; use embassy_extras::unborrow;
pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
use core::ptr;
impl WordSize { impl WordSize {
fn ds(&self) -> spi::vals::Ds { fn ds(&self) -> spi::vals::Ds {
@ -166,10 +166,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T> {
} }
unsafe { unsafe {
let dr = regs.dr().ptr() as *mut u8; let dr = regs.dr().ptr() as *mut u8;
ptr::write_volatile( ptr::write_volatile(dr, *word);
dr,
*word,
);
} }
loop { loop {
let sr = unsafe { regs.sr().read() }; let sr = unsafe { regs.sr().read() };
@ -205,10 +202,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> {
} }
unsafe { unsafe {
let dr = regs.dr().ptr() as *mut u8; let dr = regs.dr().ptr() as *mut u8;
ptr::write_volatile( ptr::write_volatile(dr, *word);
dr,
*word,
);
} }
loop { loop {
let sr = unsafe { regs.sr().read() }; let sr = unsafe { regs.sr().read() };
@ -227,9 +221,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> {
} }
unsafe { unsafe {
let dr = regs.rxdr().ptr() as *const u8; let dr = regs.rxdr().ptr() as *const u8;
*word = ptr::read_volatile( *word = ptr::read_volatile(dr);
dr
);
} }
let sr = unsafe { regs.sr().read() }; let sr = unsafe { regs.sr().read() };
if sr.fre() { if sr.fre() {
@ -260,10 +252,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T> {
} }
unsafe { unsafe {
let dr = regs.dr().ptr() as *mut u16; let dr = regs.dr().ptr() as *mut u16;
ptr::write_volatile( ptr::write_volatile(dr, *word);
dr,
*word,
);
} }
loop { loop {
let sr = unsafe { regs.sr().read() }; let sr = unsafe { regs.sr().read() };
@ -299,19 +288,14 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T>
} }
unsafe { unsafe {
let dr = regs.dr().ptr() as *mut u16; let dr = regs.dr().ptr() as *mut u16;
ptr::write_volatile( ptr::write_volatile(dr, *word);
dr,
*word,
);
} }
while unsafe { !regs.sr().read().rxne() } { while unsafe { !regs.sr().read().rxne() } {
// spin waiting for inbound to shift in. // spin waiting for inbound to shift in.
} }
unsafe { unsafe {
let dr = regs.rxdr().ptr() as *const u16; let dr = regs.rxdr().ptr() as *const u16;
*word = ptr::read_volatile( *word = ptr::read_volatile(dr);
dr
);
} }
let sr = unsafe { regs.sr().read() }; let sr = unsafe { regs.sr().read() };
if sr.fre() { if sr.fre() {

51
embassy-stm32/src/spi/v3.rs
View File

@ -7,11 +7,10 @@ use crate::pac::spi;
use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize}; use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize};
use crate::time::Hertz; use crate::time::Hertz;
use core::marker::PhantomData; use core::marker::PhantomData;
use core::ptr;
use embassy::util::Unborrow; use embassy::util::Unborrow;
use embassy_extras::unborrow; use embassy_extras::unborrow;
pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
use core::ptr;
impl WordSize { impl WordSize {
fn dsize(&self) -> u8 { fn dsize(&self) -> u8 {
@ -40,15 +39,15 @@ pub struct Spi<'d, T: Instance> {
impl<'d, T: Instance> Spi<'d, T> { impl<'d, T: Instance> Spi<'d, T> {
pub fn new<F>( pub fn new<F>(
pclk: Hertz, pclk: Hertz,
peri: impl Unborrow<Target=T> + 'd, peri: impl Unborrow<Target = T> + 'd,
sck: impl Unborrow<Target=impl SckPin<T>>, sck: impl Unborrow<Target = impl SckPin<T>>,
mosi: impl Unborrow<Target=impl MosiPin<T>>, mosi: impl Unborrow<Target = impl MosiPin<T>>,
miso: impl Unborrow<Target=impl MisoPin<T>>, miso: impl Unborrow<Target = impl MisoPin<T>>,
freq: F, freq: F,
config: Config, config: Config,
) -> Self ) -> Self
where where
F: Into<Hertz>, F: Into<Hertz>,
{ {
unborrow!(peri); unborrow!(peri);
unborrow!(sck, mosi, miso); unborrow!(sck, mosi, miso);
@ -67,9 +66,7 @@ impl<'d, T: Instance> Spi<'d, T> {
let br = Self::compute_baud_rate(pclk, freq.into()); let br = Self::compute_baud_rate(pclk, freq.into());
unsafe { unsafe {
T::regs().ifcr().write(|w| { T::regs().ifcr().write(|w| w.0 = 0xffff_ffff);
w.0 = 0xffff_ffff
});
T::regs().cfg2().modify(|w| { T::regs().cfg2().modify(|w| {
//w.set_ssoe(true); //w.set_ssoe(true);
w.set_ssoe(false); w.set_ssoe(false);
@ -125,7 +122,9 @@ impl<'d, T: Instance> Spi<'d, T> {
let (afr, n_af) = if pin < 8 { (0, pin) } else { (1, pin - 8) }; let (afr, n_af) = if pin < 8 { (0, pin) } else { (1, pin - 8) };
block.moder().modify(|w| w.set_moder(pin, Moder::ALTERNATE)); block.moder().modify(|w| w.set_moder(pin, Moder::ALTERNATE));
block.afr(afr).modify(|w| w.set_afr(n_af, Afr(af_num))); block.afr(afr).modify(|w| w.set_afr(n_af, Afr(af_num)));
block.ospeedr().modify(|w| w.set_ospeedr(pin, crate::pac::gpio::vals::Ospeedr::VERYHIGHSPEED)); block
.ospeedr()
.modify(|w| w.set_ospeedr(pin, crate::pac::gpio::vals::Ospeedr::VERYHIGHSPEED));
} }
unsafe fn unconfigure_pin(block: Gpio, pin: usize) { unsafe fn unconfigure_pin(block: Gpio, pin: usize) {
@ -188,10 +187,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T> {
} }
unsafe { unsafe {
let txdr = regs.txdr().ptr() as *mut u8; let txdr = regs.txdr().ptr() as *mut u8;
ptr::write_volatile( ptr::write_volatile(txdr, *word);
txdr,
*word,
);
regs.cr1().modify(|reg| reg.set_cstart(true)); regs.cr1().modify(|reg| reg.set_cstart(true));
} }
loop { loop {
@ -233,10 +229,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> {
} }
unsafe { unsafe {
let txdr = regs.txdr().ptr() as *mut u8; let txdr = regs.txdr().ptr() as *mut u8;
ptr::write_volatile( ptr::write_volatile(txdr, *word);
txdr,
*word,
);
regs.cr1().modify(|reg| reg.set_cstart(true)); regs.cr1().modify(|reg| reg.set_cstart(true));
} }
loop { loop {
@ -257,9 +250,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> {
} }
unsafe { unsafe {
let rxdr = regs.rxdr().ptr() as *const u8; let rxdr = regs.rxdr().ptr() as *const u8;
*word = ptr::read_volatile( *word = ptr::read_volatile(rxdr);
rxdr
);
} }
let sr = unsafe { regs.sr().read() }; let sr = unsafe { regs.sr().read() };
if sr.tifre() { if sr.tifre() {
@ -290,10 +281,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T> {
} }
unsafe { unsafe {
let txdr = regs.txdr().ptr() as *mut u16; let txdr = regs.txdr().ptr() as *mut u16;
ptr::write_volatile( ptr::write_volatile(txdr, *word);
txdr,
*word,
);
regs.cr1().modify(|reg| reg.set_cstart(true)); regs.cr1().modify(|reg| reg.set_cstart(true));
} }
loop { loop {
@ -330,10 +318,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T>
} }
unsafe { unsafe {
let txdr = regs.txdr().ptr() as *mut u16; let txdr = regs.txdr().ptr() as *mut u16;
ptr::write_volatile( ptr::write_volatile(txdr, *word);
txdr,
*word,
);
regs.cr1().modify(|reg| reg.set_cstart(true)); regs.cr1().modify(|reg| reg.set_cstart(true));
} }
@ -356,9 +341,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T>
unsafe { unsafe {
let rxdr = regs.rxdr().ptr() as *const u16; let rxdr = regs.rxdr().ptr() as *const u16;
*word = ptr::read_volatile( *word = ptr::read_volatile(rxdr);
rxdr
);
} }
let sr = unsafe { regs.sr().read() }; let sr = unsafe { regs.sr().read() };
if sr.tifre() { if sr.tifre() {