From 2376b3bdfa573027c1ee4d66f8fdd6ca422a0fdd Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Mon, 13 Nov 2023 01:53:27 +0100 Subject: [PATCH] stm32/rcc: fix pll enum naming on f4, f7. --- embassy-stm32/src/rcc/f4f7.rs | 10 +++++----- examples/stm32f4/src/bin/eth.rs | 2 +- examples/stm32f4/src/bin/sdmmc.rs | 4 ++-- examples/stm32f4/src/bin/usb_ethernet.rs | 4 ++-- examples/stm32f4/src/bin/usb_raw.rs | 4 ++-- examples/stm32f4/src/bin/usb_serial.rs | 4 ++-- examples/stm32f7/src/bin/eth.rs | 2 +- examples/stm32f7/src/bin/sdmmc.rs | 4 ++-- examples/stm32f7/src/bin/usb_serial.rs | 4 ++-- tests/stm32/src/common.rs | 4 ++-- 10 files changed, 21 insertions(+), 21 deletions(-) diff --git a/embassy-stm32/src/rcc/f4f7.rs b/embassy-stm32/src/rcc/f4f7.rs index 9e8c639d..718ba9b7 100644 --- a/embassy-stm32/src/rcc/f4f7.rs +++ b/embassy-stm32/src/rcc/f4f7.rs @@ -1,7 +1,7 @@ use crate::pac::pwr::vals::Vos; pub use crate::pac::rcc::vals::{ - Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp, Pllq, Pllr, Pllsrc as PllSource, - Ppre as APBPrescaler, Sw as Sysclk, + Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, + Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk, }; use crate::pac::{FLASH, PWR, RCC}; use crate::rcc::{set_freqs, Clocks}; @@ -49,11 +49,11 @@ pub struct Pll { pub mul: PllMul, /// PLL P division factor. If None, PLL P output is disabled. - pub divp: Option, + pub divp: Option, /// PLL Q division factor. If None, PLL Q output is disabled. - pub divq: Option, + pub divq: Option, /// PLL R division factor. If None, PLL R output is disabled. - pub divr: Option, + pub divr: Option, } /// Configuration of the core clocks diff --git a/examples/stm32f4/src/bin/eth.rs b/examples/stm32f4/src/bin/eth.rs index 1747bbf4..088d83c0 100644 --- a/examples/stm32f4/src/bin/eth.rs +++ b/examples/stm32f4/src/bin/eth.rs @@ -42,7 +42,7 @@ async fn main(spawner: Spawner) -> ! { config.rcc.pll = Some(Pll { prediv: PllPreDiv::DIV4, mul: PllMul::MUL180, - divp: Some(Pllp::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz. + divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz. divq: None, divr: None, }); diff --git a/examples/stm32f4/src/bin/sdmmc.rs b/examples/stm32f4/src/bin/sdmmc.rs index 37e42384..91747b2d 100644 --- a/examples/stm32f4/src/bin/sdmmc.rs +++ b/examples/stm32f4/src/bin/sdmmc.rs @@ -30,8 +30,8 @@ async fn main(_spawner: Spawner) { config.rcc.pll = Some(Pll { prediv: PllPreDiv::DIV4, mul: PllMul::MUL168, - divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz. - divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz. + divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz. + divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz. divr: None, }); config.rcc.ahb_pre = AHBPrescaler::DIV1; diff --git a/examples/stm32f4/src/bin/usb_ethernet.rs b/examples/stm32f4/src/bin/usb_ethernet.rs index 34407b95..6bf5b1cb 100644 --- a/examples/stm32f4/src/bin/usb_ethernet.rs +++ b/examples/stm32f4/src/bin/usb_ethernet.rs @@ -56,8 +56,8 @@ async fn main(spawner: Spawner) { config.rcc.pll = Some(Pll { prediv: PllPreDiv::DIV4, mul: PllMul::MUL168, - divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz. - divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz. + divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz. + divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz. divr: None, }); config.rcc.ahb_pre = AHBPrescaler::DIV1; diff --git a/examples/stm32f4/src/bin/usb_raw.rs b/examples/stm32f4/src/bin/usb_raw.rs index 689aea4f..719b22bb 100644 --- a/examples/stm32f4/src/bin/usb_raw.rs +++ b/examples/stm32f4/src/bin/usb_raw.rs @@ -85,8 +85,8 @@ async fn main(_spawner: Spawner) { config.rcc.pll = Some(Pll { prediv: PllPreDiv::DIV4, mul: PllMul::MUL168, - divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz. - divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz. + divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz. + divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz. divr: None, }); config.rcc.ahb_pre = AHBPrescaler::DIV1; diff --git a/examples/stm32f4/src/bin/usb_serial.rs b/examples/stm32f4/src/bin/usb_serial.rs index 3e05b0ef..e2ccc914 100644 --- a/examples/stm32f4/src/bin/usb_serial.rs +++ b/examples/stm32f4/src/bin/usb_serial.rs @@ -32,8 +32,8 @@ async fn main(_spawner: Spawner) { config.rcc.pll = Some(Pll { prediv: PllPreDiv::DIV4, mul: PllMul::MUL168, - divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz. - divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz. + divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz. + divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz. divr: None, }); config.rcc.ahb_pre = AHBPrescaler::DIV1; diff --git a/examples/stm32f7/src/bin/eth.rs b/examples/stm32f7/src/bin/eth.rs index 7c6c419a..dd006944 100644 --- a/examples/stm32f7/src/bin/eth.rs +++ b/examples/stm32f7/src/bin/eth.rs @@ -43,7 +43,7 @@ async fn main(spawner: Spawner) -> ! { config.rcc.pll = Some(Pll { prediv: PllPreDiv::DIV4, mul: PllMul::MUL216, - divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz + divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz divq: None, divr: None, }); diff --git a/examples/stm32f7/src/bin/sdmmc.rs b/examples/stm32f7/src/bin/sdmmc.rs index 430aa781..990de0ab 100644 --- a/examples/stm32f7/src/bin/sdmmc.rs +++ b/examples/stm32f7/src/bin/sdmmc.rs @@ -26,8 +26,8 @@ async fn main(_spawner: Spawner) { config.rcc.pll = Some(Pll { prediv: PllPreDiv::DIV4, mul: PllMul::MUL216, - divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz - divq: Some(Pllq::DIV9), // 8mhz / 4 * 216 / 9 = 48Mhz + divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz + divq: Some(PllQDiv::DIV9), // 8mhz / 4 * 216 / 9 = 48Mhz divr: None, }); config.rcc.ahb_pre = AHBPrescaler::DIV1; diff --git a/examples/stm32f7/src/bin/usb_serial.rs b/examples/stm32f7/src/bin/usb_serial.rs index 6aca732b..4991edbf 100644 --- a/examples/stm32f7/src/bin/usb_serial.rs +++ b/examples/stm32f7/src/bin/usb_serial.rs @@ -32,8 +32,8 @@ async fn main(_spawner: Spawner) { config.rcc.pll = Some(Pll { prediv: PllPreDiv::DIV4, mul: PllMul::MUL216, - divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz - divq: Some(Pllq::DIV9), // 8mhz / 4 * 216 / 9 = 48Mhz + divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz + divq: Some(PllQDiv::DIV9), // 8mhz / 4 * 216 / 9 = 48Mhz divr: None, }); config.rcc.ahb_pre = AHBPrescaler::DIV1; diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs index e7367d5e..fe694cbe 100644 --- a/tests/stm32/src/common.rs +++ b/tests/stm32/src/common.rs @@ -271,7 +271,7 @@ pub fn config() -> Config { config.rcc.pll = Some(Pll { prediv: PllPreDiv::DIV4, mul: PllMul::MUL180, - divp: Some(Pllp::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz. + divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz. divq: None, divr: None, }); @@ -292,7 +292,7 @@ pub fn config() -> Config { config.rcc.pll = Some(Pll { prediv: PllPreDiv::DIV4, mul: PllMul::MUL216, - divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz. + divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz. divq: None, divr: None, });