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STM32 DAC: Disable circular writes with GPDMA as it doesn't yet support circular transfers

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Adam Greig 2023-11-19 13:57:19 +00:00 committed by Dario Nieuwenhuis
parent 31fc337e2f
commit 267cbaebe6
1 changed files with 2 additions and 0 deletions
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embassy-stm32/src/dac/mod.rs
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@ -238,6 +238,7 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
/// Note that for performance reasons in circular mode the transfer complete interrupt is disabled. /// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
/// ///
/// **Important:** Channel 1 has to be configured for the DAC instance! /// **Important:** Channel 1 has to be configured for the DAC instance!
#[cfg(not(gpdma))]
pub async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error> pub async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
where where
Tx: DmaCh1<T>, Tx: DmaCh1<T>,
@ -349,6 +350,7 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
/// Note that for performance reasons in circular mode the transfer complete interrupt is disabled. /// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
/// ///
/// **Important:** Channel 2 has to be configured for the DAC instance! /// **Important:** Channel 2 has to be configured for the DAC instance!
#[cfg(not(gpdma))]
pub async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error> pub async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
where where
Tx: DmaCh2<T>, Tx: DmaCh2<T>,