stm32: fix refcounts for usart, spi, and i2c

This commit is contained in:
xoviat
2023-09-04 15:47:33 -05:00
parent 3466c9cfa9
commit 274f63a879
7 changed files with 60 additions and 17 deletions

View File

@ -339,6 +339,12 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
}
}
impl<'d, T: Instance, TXDMA, RXDMA> Drop for I2c<'d, T, TXDMA, RXDMA> {
fn drop(&mut self) {
T::disable();
}
}
impl<'d, T: Instance> embedded_hal_02::blocking::i2c::Read for I2c<'d, T> {
type Error = Error;

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@ -838,6 +838,12 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
}
}
impl<'d, T: Instance, TXDMA, RXDMA> Drop for I2c<'d, T, TXDMA, RXDMA> {
fn drop(&mut self) {
T::disable();
}
}
mod eh02 {
use super::*;

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@ -646,6 +646,8 @@ impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> {
self.sck.as_ref().map(|x| x.set_as_disconnected());
self.mosi.as_ref().map(|x| x.set_as_disconnected());
self.miso.as_ref().map(|x| x.set_as_disconnected());
T::disable();
}
}

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@ -124,6 +124,8 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> {
rx_buffer: &'d mut [u8],
config: Config,
) -> BufferedUart<'d, T> {
// UartRx and UartTx have one refcount ea.
T::enable();
T::enable();
T::reset();
@ -143,6 +145,8 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> {
) -> BufferedUart<'d, T> {
into_ref!(cts, rts);
// UartRx and UartTx have one refcount ea.
T::enable();
T::enable();
T::reset();
@ -169,6 +173,8 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> {
) -> BufferedUart<'d, T> {
into_ref!(de);
// UartRx and UartTx have one refcount ea.
T::enable();
T::enable();
T::reset();
@ -382,6 +388,8 @@ impl<'d, T: BasicInstance> Drop for BufferedUartRx<'d, T> {
T::Interrupt::disable();
}
}
T::disable();
}
}
@ -397,6 +405,8 @@ impl<'d, T: BasicInstance> Drop for BufferedUartTx<'d, T> {
T::Interrupt::disable();
}
}
T::disable();
}
}

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@ -618,6 +618,18 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
}
}
impl<'d, T: BasicInstance, TxDma> Drop for UartTx<'d, T, TxDma> {
fn drop(&mut self) {
T::disable();
}
}
impl<'d, T: BasicInstance, TxDma> Drop for UartRx<'d, T, TxDma> {
fn drop(&mut self) {
T::disable();
}
}
impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
pub fn new(
peri: impl Peripheral<P = T> + 'd,
@ -628,6 +640,8 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
rx_dma: impl Peripheral<P = RxDma> + 'd,
config: Config,
) -> Self {
// UartRx and UartTx have one refcount ea.
T::enable();
T::enable();
T::reset();
@ -647,6 +661,8 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
) -> Self {
into_ref!(cts, rts);
// UartRx and UartTx have one refcount ea.
T::enable();
T::enable();
T::reset();
@ -672,6 +688,8 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
) -> Self {
into_ref!(de);
// UartRx and UartTx have one refcount ea.
T::enable();
T::enable();
T::reset();

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@ -1,4 +1,5 @@
use core::future::poll_fn;
use core::mem;
use core::sync::atomic::{compiler_fence, Ordering};
use core::task::Poll;
@ -24,12 +25,16 @@ impl<'d, T: BasicInstance, RxDma: super::RxDma<T>> UartRx<'d, T, RxDma> {
let request = self.rx_dma.request();
let opts = Default::default();
let ring_buf = unsafe { ReadableRingBuffer::new_read(self.rx_dma, request, rdr(T::regs()), dma_buf, opts) };
// Safety: we forget the struct before this function returns.
let rx_dma = unsafe { self.rx_dma.clone_unchecked() };
let _peri = unsafe { self._peri.clone_unchecked() };
RingBufferedUartRx {
_peri: self._peri,
ring_buf,
}
let ring_buf = unsafe { ReadableRingBuffer::new_read(rx_dma, request, rdr(T::regs()), dma_buf, opts) };
// Don't disable the clock
mem::forget(self);
RingBufferedUartRx { _peri, ring_buf }
}
}
@ -186,6 +191,8 @@ impl<'d, T: BasicInstance, RxDma: super::RxDma<T>> RingBufferedUartRx<'d, T, RxD
impl<T: BasicInstance, RxDma: super::RxDma<T>> Drop for RingBufferedUartRx<'_, T, RxDma> {
fn drop(&mut self) {
self.teardown_uart();
T::disable();
}
}
/// Return an error result if the Sr register has errors