From d0d8585e4cdb73373ead13289a28b7d155377963 Mon Sep 17 00:00:00 2001 From: shakencodes Date: Wed, 1 Nov 2023 11:46:17 -0700 Subject: [PATCH 1/4] Reinstate rcc::Config adc_clock_source field --- embassy-stm32/src/rcc/l4l5.rs | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/embassy-stm32/src/rcc/l4l5.rs b/embassy-stm32/src/rcc/l4l5.rs index 2f89f682..a7c136a3 100644 --- a/embassy-stm32/src/rcc/l4l5.rs +++ b/embassy-stm32/src/rcc/l4l5.rs @@ -4,8 +4,8 @@ pub use crate::pac::rcc::vals::Clk48sel as Clk48Src; #[cfg(any(stm32wb, stm32wl))] pub use crate::pac::rcc::vals::Hsepre as HsePrescaler; pub use crate::pac::rcc::vals::{ - Hpre as AHBPrescaler, Msirange as MSIRange, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, - Pllr as PllRDiv, Pllsrc as PLLSource, Ppre as APBPrescaler, Sw as ClockSrc, + Adcsel, Hpre as AHBPrescaler, Msirange as MSIRange, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, + Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc as PLLSource, Ppre as APBPrescaler, Sw as ClockSrc, }; use crate::pac::{FLASH, RCC}; use crate::rcc::{set_freqs, Clocks}; @@ -52,7 +52,30 @@ pub struct Pll { pub divr: Option, } -/// Clocks configutation +#[derive(Clone, Copy)] +pub enum AdcClockSource { + HSI16, + PLLPCLK, + SYSCLK, +} + +impl AdcClockSource { + pub fn adcsel(&self) -> Adcsel { + match self { + AdcClockSource::HSI16 => Adcsel::HSI, + AdcClockSource::PLLPCLK => Adcsel::PLL1_P, + AdcClockSource::SYSCLK => Adcsel::SYS, + } + } +} + +impl Default for AdcClockSource { + fn default() -> Self { + Self::HSI16 + } +} + +/// Clocks configuration pub struct Config { // base clock sources pub msi: Option, @@ -84,6 +107,8 @@ pub struct Config { // low speed LSI/LSE/RTC pub ls: super::LsConfig, + + pub adc_clock_source: AdcClockSource, } impl Default for Config { @@ -111,6 +136,7 @@ impl Default for Config { #[cfg(any(stm32l4, stm32l5, stm32wb))] clk48_src: Clk48Src::HSI48, ls: Default::default(), + adc_clock_source: AdcClockSource::default(), } } } @@ -344,6 +370,8 @@ pub(crate) unsafe fn init(config: Config) { }); while RCC.cfgr().read().sws() != config.mux {} + RCC.ccipr().modify(|w| w.set_adcsel(config.adc_clock_source.adcsel())); + #[cfg(any(stm32wl, stm32wb))] { RCC.extcfgr().modify(|w| { From e2688dda22a813fdcf7938ef7ca003be4c94c0c2 Mon Sep 17 00:00:00 2001 From: shakencodes Date: Wed, 1 Nov 2023 12:06:19 -0700 Subject: [PATCH 2/4] Eliminates redefinition of AdcClockSource --- embassy-stm32/src/rcc/l4l5.rs | 31 ++++--------------------------- 1 file changed, 4 insertions(+), 27 deletions(-) diff --git a/embassy-stm32/src/rcc/l4l5.rs b/embassy-stm32/src/rcc/l4l5.rs index a7c136a3..78b8e060 100644 --- a/embassy-stm32/src/rcc/l4l5.rs +++ b/embassy-stm32/src/rcc/l4l5.rs @@ -4,8 +4,8 @@ pub use crate::pac::rcc::vals::Clk48sel as Clk48Src; #[cfg(any(stm32wb, stm32wl))] pub use crate::pac::rcc::vals::Hsepre as HsePrescaler; pub use crate::pac::rcc::vals::{ - Adcsel, Hpre as AHBPrescaler, Msirange as MSIRange, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, - Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc as PLLSource, Ppre as APBPrescaler, Sw as ClockSrc, + Adcsel as AdcClockSource, Hpre as AHBPrescaler, Msirange as MSIRange, Pllm as PllPreDiv, Plln as PllMul, + Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc as PLLSource, Ppre as APBPrescaler, Sw as ClockSrc, }; use crate::pac::{FLASH, RCC}; use crate::rcc::{set_freqs, Clocks}; @@ -52,29 +52,6 @@ pub struct Pll { pub divr: Option, } -#[derive(Clone, Copy)] -pub enum AdcClockSource { - HSI16, - PLLPCLK, - SYSCLK, -} - -impl AdcClockSource { - pub fn adcsel(&self) -> Adcsel { - match self { - AdcClockSource::HSI16 => Adcsel::HSI, - AdcClockSource::PLLPCLK => Adcsel::PLL1_P, - AdcClockSource::SYSCLK => Adcsel::SYS, - } - } -} - -impl Default for AdcClockSource { - fn default() -> Self { - Self::HSI16 - } -} - /// Clocks configuration pub struct Config { // base clock sources @@ -136,7 +113,7 @@ impl Default for Config { #[cfg(any(stm32l4, stm32l5, stm32wb))] clk48_src: Clk48Src::HSI48, ls: Default::default(), - adc_clock_source: AdcClockSource::default(), + adc_clock_source: AdcClockSource::HSI, } } } @@ -370,7 +347,7 @@ pub(crate) unsafe fn init(config: Config) { }); while RCC.cfgr().read().sws() != config.mux {} - RCC.ccipr().modify(|w| w.set_adcsel(config.adc_clock_source.adcsel())); + RCC.ccipr().modify(|w| w.set_adcsel(config.adc_clock_source)); #[cfg(any(stm32wl, stm32wb))] { From b4a82b7ed44cfbb9929d4c1a6357aaf6ec177ac2 Mon Sep 17 00:00:00 2001 From: shakencodes Date: Wed, 1 Nov 2023 12:48:08 -0700 Subject: [PATCH 3/4] =?UTF-8?q?Correct=20adc=5Fclock=5Fsource=20for=20all?= =?UTF-8?q?=20=C2=B5procs=20in=20l4l5.rs?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- embassy-stm32/Cargo.toml | 4 ++-- embassy-stm32/src/rcc/l4l5.rs | 5 ++++- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml index ffb70934..bc79ab7a 100644 --- a/embassy-stm32/Cargo.toml +++ b/embassy-stm32/Cargo.toml @@ -58,7 +58,7 @@ rand_core = "0.6.3" sdio-host = "0.5.0" embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true } critical-section = "1.1" -stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-bcc9b6bf9fa195e91625849efc4ba473d9ace4e9" } +stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-73b8c37ae74fc28b247188c989fd99400611bd6b" } vcell = "0.1.3" bxcan = "0.7.0" nb = "1.0.0" @@ -76,7 +76,7 @@ critical-section = { version = "1.1", features = ["std"] } [build-dependencies] proc-macro2 = "1.0.36" quote = "1.0.15" -stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-bcc9b6bf9fa195e91625849efc4ba473d9ace4e9", default-features = false, features = ["metadata"]} +stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-73b8c37ae74fc28b247188c989fd99400611bd6b", default-features = false, features = ["metadata"]} [features] diff --git a/embassy-stm32/src/rcc/l4l5.rs b/embassy-stm32/src/rcc/l4l5.rs index 78b8e060..d855d477 100644 --- a/embassy-stm32/src/rcc/l4l5.rs +++ b/embassy-stm32/src/rcc/l4l5.rs @@ -113,7 +113,7 @@ impl Default for Config { #[cfg(any(stm32l4, stm32l5, stm32wb))] clk48_src: Clk48Src::HSI48, ls: Default::default(), - adc_clock_source: AdcClockSource::HSI, + adc_clock_source: AdcClockSource::SYS, } } } @@ -347,6 +347,9 @@ pub(crate) unsafe fn init(config: Config) { }); while RCC.cfgr().read().sws() != config.mux {} + #[cfg(stm32l5)] + RCC.ccipr1().modify(|w| w.set_adcsel(config.adc_clock_source)); + #[cfg(not(stm32l5))] RCC.ccipr().modify(|w| w.set_adcsel(config.adc_clock_source)); #[cfg(any(stm32wl, stm32wb))] From bc07539133937c254930bbdafe1b01bb0f5912e3 Mon Sep 17 00:00:00 2001 From: shakencodes Date: Wed, 1 Nov 2023 13:30:04 -0700 Subject: [PATCH 4/4] Fix missed field in cfg'd code --- embassy-stm32/src/rcc/l4l5.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/embassy-stm32/src/rcc/l4l5.rs b/embassy-stm32/src/rcc/l4l5.rs index d855d477..0d052713 100644 --- a/embassy-stm32/src/rcc/l4l5.rs +++ b/embassy-stm32/src/rcc/l4l5.rs @@ -148,6 +148,7 @@ pub const WPAN_DEFAULT: Config = Config { shared_ahb_pre: AHBPrescaler::DIV1, apb1_pre: APBPrescaler::DIV1, apb2_pre: APBPrescaler::DIV1, + adc_clock_source: AdcClockSource::SYS, }; pub(crate) unsafe fn init(config: Config) {