rp: DMA behaviour during FLASH operations
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0dea7b02d6
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278818395e
@ -174,25 +174,17 @@ impl<'d, T: Instance, const FLASH_SIZE: usize> Flash<'d, T, FLASH_SIZE> {
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crate::multicore::pause_core1();
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crate::multicore::pause_core1();
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critical_section::with(|_| {
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critical_section::with(|_| {
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// Pause all DMA channels for the duration of the ram operation
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// Wait for all DMA channels in flash to finish before ram operation
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for (number, status) in dma_status.iter_mut().enumerate() {
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const SRAM_LOWER: u32 = 0x2000_0000;
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let ch = crate::pac::DMA.ch(number as _);
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for n in 0..crate::dma::CHANNEL_COUNT {
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*status = ch.ctrl_trig().read().en();
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let ch = crate::pac::DMA.ch(n);
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if *status {
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if ch.read_addr().read() < SRAM_LOWER {
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ch.ctrl_trig().modify(|w| w.set_en(false));
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while ch.ctrl_trig().read().busy() {}
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}
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}
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}
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}
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// Run our flash operation in RAM
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// Run our flash operation in RAM
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operation();
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operation();
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// Re-enable previously enabled DMA channels
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for (number, status) in dma_status.iter().enumerate() {
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let ch = crate::pac::DMA.ch(number as _);
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if *status {
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ch.ctrl_trig().modify(|w| w.set_en(true));
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}
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}
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});
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});
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// Resume CORE1 execution
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// Resume CORE1 execution
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