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stm32/rtc: restructure

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This commit is contained in:
xoviat 2023-08-06 11:58:28 -05:00
parent 66c1712118
commit 28618d12a1
4 changed files with 35 additions and 40 deletions
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2
embassy-stm32/src/rcc/wb.rs
View File

@ -1,6 +1,6 @@
pub use super::common::{AHBPrescaler, APBPrescaler};
use crate::rcc::Clocks;
use crate::rtc::{enable_rtc, RtcClockSource};
use crate::rtc::{enable as enable_rtc, RtcClockSource};
use crate::time::{khz, mhz, Hertz};
/// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC,

33
embassy-stm32/src/rtc/mod.rs
View File

@ -33,19 +33,15 @@ pub struct Rtc<'d, T: Instance> {
rtc_config: RtcConfig,
}
pub(crate) fn enable_rtc(clock_source: RtcClockSource) {
// TODO: rewrite the RTC module so that enable is separated from configure
#[allow(dead_code)]
pub(crate) fn enable(clock_source: RtcClockSource) {
Rtc::<crate::peripherals::RTC>::enable(clock_source);
}
assert!(clock_source == RtcClockSource::LSI || clock_source == RtcClockSource::LSE);
let _ = Rtc::new(
unsafe { crate::Peripherals::steal().RTC },
RtcConfig {
clock_config: clock_source,
async_prescaler: 1,
sync_prescaler: 1,
},
);
#[cfg(feature = "time")]
#[allow(dead_code)]
pub(crate) fn set_wakeup_timer(_duration: embassy_time::Duration) {
todo!()
}
#[derive(Copy, Clone, Debug, PartialEq)]
@ -64,7 +60,7 @@ pub enum RtcClockSource {
#[derive(Copy, Clone, PartialEq)]
pub struct RtcConfig {
/// RTC clock source
clock_config: RtcClockSource,
clock_source: RtcClockSource,
/// Asynchronous prescaler factor
/// This is the asynchronous division factor:
/// ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)
@ -82,7 +78,7 @@ impl Default for RtcConfig {
/// Raw sub-seconds in 1/256.
fn default() -> Self {
RtcConfig {
clock_config: RtcClockSource::LSI,
clock_source: RtcClockSource::LSI,
async_prescaler: 127,
sync_prescaler: 255,
}
@ -91,8 +87,8 @@ impl Default for RtcConfig {
impl RtcConfig {
/// Sets the clock source of RTC config
pub fn clock_config(mut self, cfg: RtcClockSource) -> Self {
self.clock_config = cfg;
pub fn clock_source(mut self, clock_source: RtcClockSource) -> Self {
self.clock_source = clock_source;
self
}
@ -135,7 +131,10 @@ impl<'d, T: Instance> Rtc<'d, T> {
rtc_config,
};
rtc_struct.apply_config(rtc_config);
Self::enable(rtc_config.clock_source);
rtc_struct.configure(rtc_config);
rtc_struct.rtc_config = rtc_config;
rtc_struct
}

21
embassy-stm32/src/rtc/v2.rs
View File

@ -1,15 +1,10 @@
use stm32_metapac::rtc::vals::{Init, Osel, Pol};
use super::{sealed, Instance, RtcConfig};
use super::{sealed, Instance, RtcClockSource, RtcConfig};
use crate::pac::rtc::Rtc;
impl<'d, T: Instance> super::Rtc<'d, T> {
/// Applies the RTC config
/// It this changes the RTC clock source the time will be reset
pub(super) fn apply_config(&mut self, rtc_config: RtcConfig) {
// Unlock the backup domain
let clock_config = rtc_config.clock_config as u8;
pub(super) fn enable(clock_source: RtcClockSource) {
#[cfg(not(rtc_v2wb))]
use stm32_metapac::rcc::vals::Rtcsel;
@ -38,7 +33,7 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
#[cfg(not(rtc_v2wb))]
let rtcsel = reg.rtcsel().to_bits();
if !reg.rtcen() || rtcsel != clock_config {
if !reg.rtcen() || rtcsel != clock_source as u8 {
#[cfg(not(any(rtc_v2l0, rtc_v2l1, rtc_v2f2)))]
crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true));
#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
@ -53,9 +48,9 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
// Select RTC source
#[cfg(not(rtc_v2wb))]
w.set_rtcsel(Rtcsel::from_bits(clock_config));
w.set_rtcsel(Rtcsel::from_bits(clock_source as u8));
#[cfg(rtc_v2wb)]
w.set_rtcsel(clock_config);
w.set_rtcsel(clock_source as u8);
w.set_rtcen(true);
// Restore bcdr
@ -71,7 +66,11 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
w.set_lsebyp(reg.lsebyp());
});
}
}
/// Applies the RTC config
/// It this changes the RTC clock source the time will be reset
pub(super) fn configure(&mut self, rtc_config: RtcConfig) {
self.write(true, |rtc| {
rtc.cr().modify(|w| {
#[cfg(rtc_v2f2)]
@ -87,8 +86,6 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
w.set_prediv_a(rtc_config.async_prescaler);
});
});
self.rtc_config = rtc_config;
}
/// Calibrate the clock drift.

19
embassy-stm32/src/rtc/v3.rs
View File

@ -1,12 +1,10 @@
use stm32_metapac::rtc::vals::{Calp, Calw16, Calw8, Fmt, Init, Key, Osel, Pol, TampalrmPu, TampalrmType};
use super::{sealed, Instance, RtcCalibrationCyclePeriod, RtcConfig};
use super::{sealed, Instance, RtcCalibrationCyclePeriod, RtcClockSource, RtcConfig};
use crate::pac::rtc::Rtc;
impl<'d, T: Instance> super::Rtc<'d, T> {
/// Applies the RTC config
/// It this changes the RTC clock source the time will be reset
pub(super) fn apply_config(&mut self, rtc_config: RtcConfig) {
pub(super) fn enable(clock_source: RtcClockSource) {
// Unlock the backup domain
#[cfg(not(any(rtc_v3u5, rcc_wl5, rcc_wle)))]
{
@ -24,11 +22,10 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
let reg = crate::pac::RCC.bdcr().read();
assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
let config_rtcsel = rtc_config.clock_config as u8;
#[cfg(not(any(rcc_wl5, rcc_wle)))]
let config_rtcsel = crate::pac::rcc::vals::Rtcsel::from_bits(config_rtcsel);
let config_rtcsel = crate::pac::rcc::vals::Rtcsel::from_bits(clock_source as u8);
if !reg.rtcen() || reg.rtcsel() != config_rtcsel {
if !reg.rtcen() || reg.rtcsel() != clock_source as u8 {
crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true));
crate::pac::RCC.bdcr().modify(|w| {
@ -36,7 +33,7 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
w.set_bdrst(false);
// Select RTC source
w.set_rtcsel(config_rtcsel);
w.set_rtcsel(clock_source as u8);
w.set_rtcen(true);
@ -49,7 +46,11 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
w.set_lsebyp(reg.lsebyp());
});
}
}
/// Applies the RTC config
/// It this changes the RTC clock source the time will be reset
pub(super) fn configure(&mut self, rtc_config: RtcConfig) {
self.write(true, |rtc| {
rtc.cr().modify(|w| {
w.set_fmt(Fmt::TWENTYFOURHOUR);
@ -69,8 +70,6 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
w.set_tampalrm_pu(TampalrmPu::NOPULLUP);
});
});
self.rtc_config = rtc_config;
}
const RTC_CALR_MIN_PPM: f32 = -487.1;