From 1b24b3bd68821ec3aae5797408611edc991a8cc4 Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Sun, 28 Nov 2021 14:07:21 +0100 Subject: [PATCH 1/2] Make ci script run on Mac OS X --- ci.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ci.sh b/ci.sh index 94370abd..b9a803bf 100755 --- a/ci.sh +++ b/ci.sh @@ -5,7 +5,7 @@ set -euo pipefail export CARGO_TARGET_DIR=$PWD/target_ci export RUSTFLAGS=-Dwarnings -find -name '*.rs' -not -path '*target*' -not -path '*stm32-metapac-gen/out/*' | xargs rustfmt --check --skip-children --unstable-features --edition 2018 +find . -name '*.rs' -not -path '*target*' -not -path '*stm32-metapac-gen/out/*' | xargs rustfmt --check --skip-children --unstable-features --edition 2018 # Generate stm32-metapac # for some reason Cargo stomps the cache if we don't specify --target. From 25b49a8a2ad151dbf827785c793f7d0bef8af489 Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Sun, 28 Nov 2021 16:46:08 +0100 Subject: [PATCH 2/2] Remove common clock types Different STM32 RCC peripherals have different capabilities and register values. Define types for each RCC types inside each module to ensure full range of capabilities for each family can be used --- embassy-stm32/src/rcc/g0/mod.rs | 25 +++++++- embassy-stm32/src/rcc/g4/mod.rs | 25 +++++++- embassy-stm32/src/rcc/l0/mod.rs | 82 ++++++++++++++++++++++++++- embassy-stm32/src/rcc/l1/mod.rs | 53 ++++++++++++++++- embassy-stm32/src/rcc/mod.rs | 1 - embassy-stm32/src/rcc/types.rs | 94 ------------------------------- embassy-stm32/src/rcc/wb/mod.rs | 35 +++++++++++- embassy-stm32/src/rcc/wl5x/mod.rs | 35 +++++++++++- 8 files changed, 249 insertions(+), 101 deletions(-) delete mode 100644 embassy-stm32/src/rcc/types.rs diff --git a/embassy-stm32/src/rcc/g0/mod.rs b/embassy-stm32/src/rcc/g0/mod.rs index c0b5b14e..103d9a84 100644 --- a/embassy-stm32/src/rcc/g0/mod.rs +++ b/embassy-stm32/src/rcc/g0/mod.rs @@ -1,4 +1,3 @@ -pub use super::types::*; use crate::pac; use crate::peripherals::{self, RCC}; use crate::rcc::{get_freqs, set_freqs, Clocks}; @@ -49,6 +48,30 @@ impl Into for HSI16Prescaler { } } +/// AHB prescaler +#[derive(Clone, Copy, PartialEq)] +pub enum AHBPrescaler { + NotDivided, + Div2, + Div4, + Div8, + Div16, + Div64, + Div128, + Div256, + Div512, +} + +/// APB prescaler +#[derive(Clone, Copy)] +pub enum APBPrescaler { + NotDivided, + Div2, + Div4, + Div8, + Div16, +} + impl Into for APBPrescaler { fn into(self) -> u8 { match self { diff --git a/embassy-stm32/src/rcc/g4/mod.rs b/embassy-stm32/src/rcc/g4/mod.rs index b0338e72..8dd37af8 100644 --- a/embassy-stm32/src/rcc/g4/mod.rs +++ b/embassy-stm32/src/rcc/g4/mod.rs @@ -1,4 +1,3 @@ -pub use super::types::*; use crate::pac; use crate::peripherals::{self, RCC}; use crate::rcc::{get_freqs, set_freqs, Clocks}; @@ -21,6 +20,30 @@ pub enum ClockSrc { HSI16, } +/// AHB prescaler +#[derive(Clone, Copy, PartialEq)] +pub enum AHBPrescaler { + NotDivided, + Div2, + Div4, + Div8, + Div16, + Div64, + Div128, + Div256, + Div512, +} + +/// APB prescaler +#[derive(Clone, Copy)] +pub enum APBPrescaler { + NotDivided, + Div2, + Div4, + Div8, + Div16, +} + impl Into for APBPrescaler { fn into(self) -> u8 { match self { diff --git a/embassy-stm32/src/rcc/l0/mod.rs b/embassy-stm32/src/rcc/l0/mod.rs index e65faaa2..8af4eca0 100644 --- a/embassy-stm32/src/rcc/l0/mod.rs +++ b/embassy-stm32/src/rcc/l0/mod.rs @@ -1,4 +1,3 @@ -pub use super::types::*; use crate::pac; use crate::peripherals::{self, CRS, RCC, SYSCFG}; use crate::rcc::{get_freqs, set_freqs, Clocks}; @@ -24,6 +23,87 @@ pub enum ClockSrc { HSI16, } +/// MSI Clock Range +/// +/// These ranges control the frequency of the MSI. Internally, these ranges map +/// to the `MSIRANGE` bits in the `RCC_ICSCR` register. +#[derive(Clone, Copy)] +pub enum MSIRange { + /// Around 65.536 kHz + Range0, + /// Around 131.072 kHz + Range1, + /// Around 262.144 kHz + Range2, + /// Around 524.288 kHz + Range3, + /// Around 1.048 MHz + Range4, + /// Around 2.097 MHz (reset value) + Range5, + /// Around 4.194 MHz + Range6, +} + +impl Default for MSIRange { + fn default() -> MSIRange { + MSIRange::Range5 + } +} + +/// PLL divider +#[derive(Clone, Copy)] +pub enum PLLDiv { + Div2, + Div3, + Div4, +} + +/// PLL multiplier +#[derive(Clone, Copy)] +pub enum PLLMul { + Mul3, + Mul4, + Mul6, + Mul8, + Mul12, + Mul16, + Mul24, + Mul32, + Mul48, +} + +/// AHB prescaler +#[derive(Clone, Copy, PartialEq)] +pub enum AHBPrescaler { + NotDivided, + Div2, + Div4, + Div8, + Div16, + Div64, + Div128, + Div256, + Div512, +} + +/// APB prescaler +#[derive(Clone, Copy)] +pub enum APBPrescaler { + NotDivided, + Div2, + Div4, + Div8, + Div16, +} + +/// PLL clock input source +#[derive(Clone, Copy)] +pub enum PLLSource { + HSI16, + HSE(Hertz), +} + impl Into for PLLMul { fn into(self) -> Pllmul { match self { diff --git a/embassy-stm32/src/rcc/l1/mod.rs b/embassy-stm32/src/rcc/l1/mod.rs index f6edd4e4..d0b52d2f 100644 --- a/embassy-stm32/src/rcc/l1/mod.rs +++ b/embassy-stm32/src/rcc/l1/mod.rs @@ -1,4 +1,3 @@ -pub use super::types::*; use crate::pac; use crate::peripherals::{self, RCC}; use crate::rcc::{get_freqs, set_freqs, Clocks}; @@ -21,6 +20,58 @@ pub enum ClockSrc { HSI, } +/// MSI Clock Range +/// +/// These ranges control the frequency of the MSI. Internally, these ranges map +/// to the `MSIRANGE` bits in the `RCC_ICSCR` register. +#[derive(Clone, Copy)] +pub enum MSIRange { + /// Around 65.536 kHz + Range0, + /// Around 131.072 kHz + Range1, + /// Around 262.144 kHz + Range2, + /// Around 524.288 kHz + Range3, + /// Around 1.048 MHz + Range4, + /// Around 2.097 MHz (reset value) + Range5, + /// Around 4.194 MHz + Range6, +} + +impl Default for MSIRange { + fn default() -> MSIRange { + MSIRange::Range5 + } +} + +/// AHB prescaler +#[derive(Clone, Copy, PartialEq)] +pub enum AHBPrescaler { + NotDivided, + Div2, + Div4, + Div8, + Div16, + Div64, + Div128, + Div256, + Div512, +} + +/// APB prescaler +#[derive(Clone, Copy)] +pub enum APBPrescaler { + NotDivided, + Div2, + Div4, + Div8, + Div16, +} + type Ppre = u8; impl Into for APBPrescaler { fn into(self) -> Ppre { diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs index cdcbd2af..b926eb8c 100644 --- a/embassy-stm32/src/rcc/mod.rs +++ b/embassy-stm32/src/rcc/mod.rs @@ -3,7 +3,6 @@ use crate::peripherals; use crate::time::Hertz; use core::mem::MaybeUninit; -mod types; #[derive(Clone, Copy)] pub struct Clocks { diff --git a/embassy-stm32/src/rcc/types.rs b/embassy-stm32/src/rcc/types.rs deleted file mode 100644 index 1fcaa27e..00000000 --- a/embassy-stm32/src/rcc/types.rs +++ /dev/null @@ -1,94 +0,0 @@ -#![allow(dead_code)] -/// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC, -/// and with the addition of the init function to configure a system clock. -use crate::time::Hertz; - -/// System clock mux source -#[derive(Clone, Copy)] -pub enum ClockSrc { - MSI(MSIRange), - PLL(PLLSource, PLLMul, PLLDiv), - HSE(Hertz), - HSI16, -} - -/// MSI Clock Range -/// -/// These ranges control the frequency of the MSI. Internally, these ranges map -/// to the `MSIRANGE` bits in the `RCC_ICSCR` register. -#[derive(Clone, Copy)] -pub enum MSIRange { - /// Around 65.536 kHz - Range0, - /// Around 131.072 kHz - Range1, - /// Around 262.144 kHz - Range2, - /// Around 524.288 kHz - Range3, - /// Around 1.048 MHz - Range4, - /// Around 2.097 MHz (reset value) - Range5, - /// Around 4.194 MHz - Range6, -} - -impl Default for MSIRange { - fn default() -> MSIRange { - MSIRange::Range5 - } -} - -/// PLL divider -#[derive(Clone, Copy)] -pub enum PLLDiv { - Div2, - Div3, - Div4, -} - -/// PLL multiplier -#[derive(Clone, Copy)] -pub enum PLLMul { - Mul3, - Mul4, - Mul6, - Mul8, - Mul12, - Mul16, - Mul24, - Mul32, - Mul48, -} - -/// AHB prescaler -#[derive(Clone, Copy, PartialEq)] -pub enum AHBPrescaler { - NotDivided, - Div2, - Div4, - Div8, - Div16, - Div64, - Div128, - Div256, - Div512, -} - -/// APB prescaler -#[derive(Clone, Copy)] -pub enum APBPrescaler { - NotDivided, - Div2, - Div4, - Div8, - Div16, -} - -/// PLL clock input source -#[derive(Clone, Copy)] -pub enum PLLSource { - HSI16, - HSE(Hertz), -} diff --git a/embassy-stm32/src/rcc/wb/mod.rs b/embassy-stm32/src/rcc/wb/mod.rs index 4247d8ff..43535741 100644 --- a/embassy-stm32/src/rcc/wb/mod.rs +++ b/embassy-stm32/src/rcc/wb/mod.rs @@ -1,4 +1,3 @@ -pub use super::types::*; use crate::pac; use crate::peripherals::{self, RCC}; use crate::rcc::{get_freqs, set_freqs, Clocks}; @@ -23,6 +22,35 @@ pub enum ClockSrc { HSI16, } +/// AHB prescaler +#[derive(Clone, Copy, PartialEq)] +pub enum AHBPrescaler { + NotDivided, + Div2, + Div3, + Div4, + Div5, + Div6, + Div8, + Div10, + Div16, + Div32, + Div64, + Div128, + Div256, + Div512, +} + +/// APB prescaler +#[derive(Clone, Copy)] +pub enum APBPrescaler { + NotDivided, + Div2, + Div4, + Div8, + Div16, +} + impl Into for APBPrescaler { fn into(self) -> u8 { match self { @@ -40,9 +68,14 @@ impl Into for AHBPrescaler { match self { AHBPrescaler::NotDivided => 1, AHBPrescaler::Div2 => 0x08, + AHBPrescaler::Div3 => 0x01, AHBPrescaler::Div4 => 0x09, + AHBPrescaler::Div5 => 0x02, + AHBPrescaler::Div6 => 0x05, AHBPrescaler::Div8 => 0x0a, + AHBPrescaler::Div10 => 0x06, AHBPrescaler::Div16 => 0x0b, + AHBPrescaler::Div32 => 0x07, AHBPrescaler::Div64 => 0x0c, AHBPrescaler::Div128 => 0x0d, AHBPrescaler::Div256 => 0x0e, diff --git a/embassy-stm32/src/rcc/wl5x/mod.rs b/embassy-stm32/src/rcc/wl5x/mod.rs index 86fb3f58..aa49c99c 100644 --- a/embassy-stm32/src/rcc/wl5x/mod.rs +++ b/embassy-stm32/src/rcc/wl5x/mod.rs @@ -1,4 +1,3 @@ -pub use super::types::*; use crate::pac; use crate::peripherals::{self, RCC}; use crate::rcc::{get_freqs, set_freqs, Clocks}; @@ -24,6 +23,35 @@ pub enum ClockSrc { HSI16, } +/// AHB prescaler +#[derive(Clone, Copy, PartialEq)] +pub enum AHBPrescaler { + NotDivided, + Div2, + Div3, + Div4, + Div5, + Div6, + Div8, + Div10, + Div16, + Div32, + Div64, + Div128, + Div256, + Div512, +} + +/// APB prescaler +#[derive(Clone, Copy)] +pub enum APBPrescaler { + NotDivided, + Div2, + Div4, + Div8, + Div16, +} + impl Into for APBPrescaler { fn into(self) -> u8 { match self { @@ -41,9 +69,14 @@ impl Into for AHBPrescaler { match self { AHBPrescaler::NotDivided => 1, AHBPrescaler::Div2 => 0x08, + AHBPrescaler::Div3 => 0x01, AHBPrescaler::Div4 => 0x09, + AHBPrescaler::Div5 => 0x02, + AHBPrescaler::Div6 => 0x05, AHBPrescaler::Div8 => 0x0a, + AHBPrescaler::Div10 => 0x06, AHBPrescaler::Div16 => 0x0b, + AHBPrescaler::Div32 => 0x07, AHBPrescaler::Div64 => 0x0c, AHBPrescaler::Div128 => 0x0d, AHBPrescaler::Div256 => 0x0e,