From f5e2fb9a5a62f90d83ec9d312d6c471a21fbe7c6 Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Mon, 7 Jun 2021 12:03:31 +0200 Subject: [PATCH 1/5] Update to new api --- embassy-stm32/src/pwr/h7.rs | 5 +--- embassy-stm32/src/rcc/h7/mod.rs | 47 +++++++++++++++------------------ embassy-stm32/src/rcc/h7/pll.rs | 22 +++++++-------- stm32-data | 2 +- 4 files changed, 32 insertions(+), 44 deletions(-) diff --git a/embassy-stm32/src/pwr/h7.rs b/embassy-stm32/src/pwr/h7.rs index 3d83b5e8..b298408a 100644 --- a/embassy-stm32/src/pwr/h7.rs +++ b/embassy-stm32/src/pwr/h7.rs @@ -28,8 +28,6 @@ pub struct Power { impl Power { pub fn new(_peri: peripherals::PWR, enable_overdrive: bool) -> Self { - use crate::pac::rcc::vals::Apb4enrSyscfgen; - // NOTE(unsafe) we have the PWR singleton unsafe { // NB. The lower bytes of CR3 can only be written once after @@ -57,8 +55,7 @@ impl Power { VoltageScale::Scale1 } else { critical_section::with(|_| { - RCC.apb4enr() - .modify(|w| w.set_syscfgen(Apb4enrSyscfgen::ENABLED)); + RCC.apb4enr().modify(|w| w.set_syscfgen(true)); SYSCFG.pwrcr().modify(|w| w.set_oden(1)); }); diff --git a/embassy-stm32/src/rcc/h7/mod.rs b/embassy-stm32/src/rcc/h7/mod.rs index 57cdd547..f15dbe07 100644 --- a/embassy-stm32/src/rcc/h7/mod.rs +++ b/embassy-stm32/src/rcc/h7/mod.rs @@ -101,10 +101,7 @@ impl<'d> Rcc<'d> { /// achieved, but the mechanism for doing so is not yet /// implemented here. pub fn freeze(mut self, pwr: &Power) -> CoreClocks { - use crate::pac::rcc::vals::{ - Apb4enrSyscfgen, Ckpersel, D1ppre, D2ppre1, D3ppre, Hpre, Hsebyp, Hsidiv, Hsion, Lsion, - Pllsrc, Sw, - }; + use crate::pac::rcc::vals::{Ckpersel, Dppre, Hpre, Hsebyp, Hsidiv, Pllsrc, Sw}; let srcclk = self.config.hse.unwrap_or(HSI); // Available clocks let (sys_ck, sys_use_pll1_p) = self.sys_ck_setup(srcclk); @@ -132,10 +129,10 @@ impl<'d> Rcc<'d> { // do so it would need to ensure all PLLxON bits are clear // before changing the value of HSIDIV let cr = RCC.cr().read(); - assert!(cr.hsion() == Hsion::ON); + assert!(cr.hsion()); assert!(cr.hsidiv() == Hsidiv::DIV1); - RCC.csr().modify(|w| w.set_lsion(Lsion::ON)); + RCC.csr().modify(|w| w.set_lsion(true)); while !RCC.csr().read().lsirdy() {} } @@ -228,12 +225,12 @@ impl<'d> Rcc<'d> { // NOTE(unsafe) We have the RCC singleton unsafe { // Ensure CSI is on and stable - RCC.cr().modify(|w| w.set_csion(Hsion::ON)); + RCC.cr().modify(|w| w.set_csion(true)); while !RCC.cr().read().csirdy() {} // Ensure HSI48 is on and stable - RCC.cr().modify(|w| w.set_hsi48on(Hsion::ON)); - while RCC.cr().read().hsi48on() == Hsion::OFF {} + RCC.cr().modify(|w| w.set_hsi48on(true)); + while !RCC.cr().read().hsi48on() {} // XXX: support MCO ? @@ -241,7 +238,7 @@ impl<'d> Rcc<'d> { Some(hse) => { // Ensure HSE is on and stable RCC.cr().modify(|w| { - w.set_hseon(Hsion::ON); + w.set_hseon(true); w.set_hsebyp(if self.config.bypass_hse { Hsebyp::BYPASSED } else { @@ -261,25 +258,27 @@ impl<'d> Rcc<'d> { }; RCC.pllckselr().modify(|w| w.set_pllsrc(pllsrc)); + let enable_pll = |pll| { + RCC.cr().modify(|w| w.set_pllon(pll, true)); + while !RCC.cr().read().pllrdy(pll) {} + }; + if pll1_p_ck.is_some() { - RCC.cr().modify(|w| w.set_pll1on(Hsion::ON)); - while !RCC.cr().read().pll1rdy() {} + enable_pll(0); } if pll2_p_ck.is_some() { - RCC.cr().modify(|w| w.set_pll2on(Hsion::ON)); - while !RCC.cr().read().pll2rdy() {} + enable_pll(1); } if pll3_p_ck.is_some() { - RCC.cr().modify(|w| w.set_pll3on(Hsion::ON)); - while !RCC.cr().read().pll3rdy() {} + enable_pll(2); } // Core Prescaler / AHB Prescaler / APB3 Prescaler RCC.d1cfgr().modify(|w| { w.set_d1cpre(Hpre(d1cpre_bits)); - w.set_d1ppre(D1ppre(ppre3_bits)); + w.set_d1ppre(Dppre(ppre3_bits)); w.set_hpre(hpre_bits) }); // Ensure core prescaler value is valid before future lower @@ -288,12 +287,12 @@ impl<'d> Rcc<'d> { // APB1 / APB2 Prescaler RCC.d2cfgr().modify(|w| { - w.set_d2ppre1(D2ppre1(ppre1_bits)); - w.set_d2ppre2(D2ppre1(ppre2_bits)); + w.set_d2ppre1(Dppre(ppre1_bits)); + w.set_d2ppre2(Dppre(ppre2_bits)); }); // APB4 Prescaler - RCC.d3cfgr().modify(|w| w.set_d3ppre(D3ppre(ppre4_bits))); + RCC.d3cfgr().modify(|w| w.set_d3ppre(Dppre(ppre4_bits))); // Peripheral Clock (per_ck) RCC.d1ccipr().modify(|w| w.set_ckpersel(ckpersel)); @@ -312,8 +311,7 @@ impl<'d> Rcc<'d> { // IO compensation cell - Requires CSI clock and SYSCFG assert!(RCC.cr().read().csirdy()); - RCC.apb4enr() - .modify(|w| w.set_syscfgen(Apb4enrSyscfgen::ENABLED)); + RCC.apb4enr().modify(|w| w.set_syscfgen(true)); // Enable the compensation cell, using back-bias voltage code // provide by the cell. @@ -364,13 +362,10 @@ impl<'d> Rcc<'d> { /// Set `enable_dma1` to true if you do not have at least one bus master (other than the CPU) /// enable during WFI/WFE pub fn enable_debug_wfe(&mut self, _dbg: &mut peripherals::DBGMCU, enable_dma1: bool) { - use crate::pac::rcc::vals::Ahb1enrDma1en; - // NOTE(unsafe) We have exclusive access to the RCC and DBGMCU unsafe { if enable_dma1 { - RCC.ahb1enr() - .modify(|w| w.set_dma1en(Ahb1enrDma1en::ENABLED)); + RCC.ahb1enr().modify(|w| w.set_dma1en(true)); } DBGMCU.cr().modify(|w| { diff --git a/embassy-stm32/src/rcc/h7/pll.rs b/embassy-stm32/src/rcc/h7/pll.rs index 4c40d84d..d3709378 100644 --- a/embassy-stm32/src/rcc/h7/pll.rs +++ b/embassy-stm32/src/rcc/h7/pll.rs @@ -46,7 +46,7 @@ fn vco_output_divider_setup(output: u32, plln: usize) -> (u32, u32) { /// /// Must have exclusive access to the RCC register block unsafe fn vco_setup(pll_src: u32, requested_output: u32, plln: usize) -> PllConfigResults { - use crate::pac::rcc::vals::{Pll1rge, Pll1vcosel}; + use crate::pac::rcc::vals::{Pllrge, Pllvcosel}; let (vco_ck_target, pll_x_p) = vco_output_divider_setup(requested_output, plln); @@ -60,8 +60,8 @@ unsafe fn vco_setup(pll_src: u32, requested_output: u32, plln: usize) -> PllConf assert!((1_000_000..=2_000_000).contains(&ref_x_ck)); RCC.pllcfgr().modify(|w| { - w.set_pllvcosel(plln, Pll1vcosel::MEDIUMVCO); - w.set_pllrge(plln, Pll1rge::RANGE1); + w.set_pllvcosel(plln, Pllvcosel::MEDIUMVCO); + w.set_pllrge(plln, Pllrge::RANGE1); }); PllConfigResults { ref_x_ck, @@ -79,7 +79,7 @@ pub(super) unsafe fn pll_setup( config: &PllConfig, plln: usize, ) -> (Option, Option, Option) { - use crate::pac::rcc::vals::{Divp1, Divp1en, Pll1fracen}; + use crate::pac::rcc::vals::Divp; match config.p_ck { Some(requested_output) => { @@ -101,22 +101,19 @@ pub(super) unsafe fn pll_setup( .modify(|w| w.set_divn1((pll_x_n - 1) as u16)); // No FRACN - RCC.pllcfgr() - .modify(|w| w.set_pllfracen(plln, Pll1fracen::RESET)); + RCC.pllcfgr().modify(|w| w.set_pllfracen(plln, false)); let vco_ck = ref_x_ck * pll_x_n; RCC.plldivr(plln) - .modify(|w| w.set_divp1(Divp1((pll_x_p - 1) as u8))); - RCC.pllcfgr() - .modify(|w| w.set_divpen(plln, Divp1en::ENABLED)); + .modify(|w| w.set_divp1(Divp((pll_x_p - 1) as u8))); + RCC.pllcfgr().modify(|w| w.set_divpen(plln, true)); // Calulate additional output dividers let q_ck = match config.q_ck { Some(Hertz(ck)) if ck > 0 => { let div = (vco_ck + ck - 1) / ck; RCC.plldivr(plln).modify(|w| w.set_divq1((div - 1) as u8)); - RCC.pllcfgr() - .modify(|w| w.set_divqen(plln, Divp1en::ENABLED)); + RCC.pllcfgr().modify(|w| w.set_divqen(plln, true)); Some(vco_ck / div) } _ => None, @@ -125,8 +122,7 @@ pub(super) unsafe fn pll_setup( Some(Hertz(ck)) if ck > 0 => { let div = (vco_ck + ck - 1) / ck; RCC.plldivr(plln).modify(|w| w.set_divr1((div - 1) as u8)); - RCC.pllcfgr() - .modify(|w| w.set_divren(plln, Divp1en::ENABLED)); + RCC.pllcfgr().modify(|w| w.set_divren(plln, true)); Some(vco_ck / div) } _ => None, diff --git a/stm32-data b/stm32-data index 33dfa674..ba3d77f5 160000 --- a/stm32-data +++ b/stm32-data @@ -1 +1 @@ -Subproject commit 33dfa674865b1b5f0bfb86f3217055a6a057a6fb +Subproject commit ba3d77f554adf361fbd4b68d256e3c631dbae528 From 1cd2c55b7cd72ac12ca3f06e581eda9216c336c0 Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Mon, 7 Jun 2021 12:19:09 +0200 Subject: [PATCH 2/5] Fix stm32l0 build --- embassy-stm32/src/clock.rs | 2 +- embassy-stm32/src/rcc/l0/mod.rs | 37 +++++++++++++++------------------ 2 files changed, 18 insertions(+), 21 deletions(-) diff --git a/embassy-stm32/src/clock.rs b/embassy-stm32/src/clock.rs index 075b8011..7f478e79 100644 --- a/embassy-stm32/src/clock.rs +++ b/embassy-stm32/src/clock.rs @@ -83,7 +83,7 @@ impl Clock { unsafe { let rcc = crate::pac::RCC; rcc.apb1enr() - .modify(|w| w.set_tim2en(crate::pac::rcc::vals::Lptimen::ENABLED)); + .modify(|w| w.set_tim2en(true)); rcc.apb1rstr().modify(|w| w.set_tim2rst(true)); rcc.apb1rstr().modify(|w| w.set_tim2rst(false)); } diff --git a/embassy-stm32/src/rcc/l0/mod.rs b/embassy-stm32/src/rcc/l0/mod.rs index a8be7203..1d920104 100644 --- a/embassy-stm32/src/rcc/l0/mod.rs +++ b/embassy-stm32/src/rcc/l0/mod.rs @@ -7,9 +7,7 @@ use core::marker::PhantomData; use embassy::util::Unborrow; use embassy_extras::unborrow; use pac::dbg::vals::{DbgSleep, DbgStandby, DbgStop}; -use pac::rcc::vals::{ - Crypen, Dbgen, Hpre, Iophen, Lptimen, Msirange, Plldiv, Pllmul, Pllon, Pllsrc, Ppre, Sw, -}; +use pac::rcc::vals::{Hpre, Msirange, Plldiv, Pllmul, Pllsrc, Ppre, Sw}; /// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC, /// and with the addition of the init function to configure a system clock. @@ -266,7 +264,7 @@ impl<'d> Rcc<'d> { // NOTE(unsafe) We have exclusive access to the RCC and DBGMCU unsafe { if enable_dma { - pac::RCC.ahbenr().modify(|w| w.set_dmaen(Crypen::ENABLED)); + pac::RCC.ahbenr().modify(|w| w.set_dmaen(true)); } pac::DBGMCU.cr().modify(|w| { @@ -285,14 +283,14 @@ impl<'d> Rcc<'d> { rcc.apb2rstr().modify(|w| w.set_syscfgrst(false)); // Enable SYSCFG peripheral - rcc.apb2enr().modify(|w| w.set_syscfgen(Dbgen::ENABLED)); + rcc.apb2enr().modify(|w| w.set_syscfgen(true)); // Reset CRS peripheral rcc.apb1rstr().modify(|w| w.set_crsrst(true)); rcc.apb1rstr().modify(|w| w.set_crsrst(false)); // Enable CRS peripheral - rcc.apb1enr().modify(|w| w.set_crsen(Lptimen::ENABLED)); + rcc.apb1enr().modify(|w| w.set_crsen(true)); // Initialize CRS let crs = pac::CRS; @@ -369,7 +367,7 @@ impl RccExt for RCC { // Enable MSI unsafe { - rcc.cr().write(|w| w.set_msion(Pllon::ENABLED)); + rcc.cr().write(|w| w.set_msion(true)); while !rcc.cr().read().msirdy() {} } @@ -379,7 +377,7 @@ impl RccExt for RCC { ClockSrc::HSI16 => { // Enable HSI16 unsafe { - rcc.cr().write(|w| w.set_hsi16on(Pllon::ENABLED)); + rcc.cr().write(|w| w.set_hsi16on(true)); while !rcc.cr().read().hsi16rdyf() {} } @@ -388,7 +386,7 @@ impl RccExt for RCC { ClockSrc::HSE(freq) => { // Enable HSE unsafe { - rcc.cr().write(|w| w.set_hseon(Pllon::ENABLED)); + rcc.cr().write(|w| w.set_hseon(true)); while !rcc.cr().read().hserdy() {} } @@ -399,7 +397,7 @@ impl RccExt for RCC { PLLSource::HSE(freq) => { // Enable HSE unsafe { - rcc.cr().write(|w| w.set_hseon(Pllon::ENABLED)); + rcc.cr().write(|w| w.set_hseon(true)); while !rcc.cr().read().hserdy() {} } freq.0 @@ -407,7 +405,7 @@ impl RccExt for RCC { PLLSource::HSI16 => { // Enable HSI unsafe { - rcc.cr().write(|w| w.set_hsi16on(Pllon::ENABLED)); + rcc.cr().write(|w| w.set_hsi16on(true)); while !rcc.cr().read().hsi16rdyf() {} } HSI_FREQ @@ -416,7 +414,7 @@ impl RccExt for RCC { // Disable PLL unsafe { - rcc.cr().modify(|w| w.set_pllon(Pllon::DISABLED)); + rcc.cr().modify(|w| w.set_pllon(false)); while rcc.cr().read().pllrdy() {} } @@ -447,7 +445,7 @@ impl RccExt for RCC { }); // Enable PLL - rcc.cr().modify(|w| w.set_pllon(Pllon::ENABLED)); + rcc.cr().modify(|w| w.set_pllon(true)); while !rcc.cr().read().pllrdy() {} } @@ -526,14 +524,13 @@ pub struct LSE(()); pub unsafe fn init(config: Config) { let rcc = pac::RCC; - let enabled = Iophen::ENABLED; rcc.iopenr().write(|w| { - w.set_iopaen(enabled); - w.set_iopben(enabled); - w.set_iopcen(enabled); - w.set_iopden(enabled); - w.set_iopeen(enabled); - w.set_iophen(enabled); + w.set_iopaen(true); + w.set_iopben(true); + w.set_iopcen(true); + w.set_iopden(true); + w.set_iopeen(true); + w.set_iophen(true); }); let r = ::steal(); From f3bb348f2aea8fa44dec1b6ef953d9d9900dc820 Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Mon, 7 Jun 2021 12:22:19 +0200 Subject: [PATCH 3/5] Update ref --- stm32-data | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/stm32-data b/stm32-data index ba3d77f5..6cc69700 160000 --- a/stm32-data +++ b/stm32-data @@ -1 +1 @@ -Subproject commit ba3d77f554adf361fbd4b68d256e3c631dbae528 +Subproject commit 6cc69700e38459c6432b02e31831c252c4dbf606 From f24c38f2a4ae6e439da2aae34062299c0383ca82 Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Mon, 7 Jun 2021 13:51:06 +0200 Subject: [PATCH 4/5] Fix --- embassy-stm32/src/dac/v2.rs | 3 ++- stm32-data | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/embassy-stm32/src/dac/v2.rs b/embassy-stm32/src/dac/v2.rs index d8c9415b..25a87db0 100644 --- a/embassy-stm32/src/dac/v2.rs +++ b/embassy-stm32/src/dac/v2.rs @@ -5,7 +5,8 @@ use core::marker::PhantomData; use embassy::util::Unborrow; use embassy_extras::unborrow; -#[derive(Debug, defmt::Format)] +#[derive(Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Error { UnconfiguredChannel, InvalidValue, diff --git a/stm32-data b/stm32-data index 6cc69700..ced687a3 160000 --- a/stm32-data +++ b/stm32-data @@ -1 +1 @@ -Subproject commit 6cc69700e38459c6432b02e31831c252c4dbf606 +Subproject commit ced687a382fa8b641af568dadc71af7abe62d5cd From a63388874a15eb6d9358801499e9164f3068a830 Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Mon, 7 Jun 2021 14:06:54 +0200 Subject: [PATCH 5/5] Update after name fix --- embassy-stm32/src/rcc/l0/mod.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/embassy-stm32/src/rcc/l0/mod.rs b/embassy-stm32/src/rcc/l0/mod.rs index 1d920104..ac32a6c4 100644 --- a/embassy-stm32/src/rcc/l0/mod.rs +++ b/embassy-stm32/src/rcc/l0/mod.rs @@ -457,8 +457,8 @@ impl RccExt for RCC { rcc.cfgr().modify(|w| { w.set_sw(sw.into()); w.set_hpre(cfgr.ahb_pre.into()); - w.set_ppre(0, cfgr.apb1_pre.into()); - w.set_ppre(1, cfgr.apb2_pre.into()); + w.set_ppre1(cfgr.apb1_pre.into()); + w.set_ppre2(cfgr.apb2_pre.into()); }); }