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Merge pull request #7 from akiles/irq

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Owned IRQs
This commit is contained in:
Dario Nieuwenhuis 2020-12-29 15:32:23 +01:00 committed by GitHub
commit 2bf9b14ef0
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GPG Key ID: 4AEE18F83AFDEB23
15 changed files with 460 additions and 156 deletions
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62
embassy-macros/src/lib.rs
View File

@ -98,3 +98,65 @@ pub fn task(args: TokenStream, item: TokenStream) -> TokenStream {
};
result.into()
}
#[proc_macro]
pub fn interrupt_declare(item: TokenStream) -> TokenStream {
let name = syn::parse_macro_input!(item as syn::Ident);
let name = format_ident!("{}", name);
let name_interrupt = format_ident!("{}Interrupt", name);
let name_handler = format!("__EMBASSY_{}_HANDLER", name);
let result = quote! {
#[allow(non_camel_case_types)]
pub struct #name_interrupt(());
unsafe impl OwnedInterrupt for #name_interrupt {
type Priority = Priority;
fn number(&self) -> u8 {
Interrupt::#name as u8
}
unsafe fn __handler(&self) -> &'static ::core::sync::atomic::AtomicPtr<u32> {
#[export_name = #name_handler]
static HANDLER: ::core::sync::atomic::AtomicPtr<u32> = ::core::sync::atomic::AtomicPtr::new(::core::ptr::null_mut());
&HANDLER
}
}
};
result.into()
}
#[proc_macro]
pub fn interrupt_take(item: TokenStream) -> TokenStream {
let name = syn::parse_macro_input!(item as syn::Ident);
let name = format!("{}", name);
let name_interrupt = format_ident!("{}Interrupt", name);
let name_handler = format!("__EMBASSY_{}_HANDLER", name);
let result = quote! {
{
#[allow(non_snake_case)]
#[export_name = #name]
pub unsafe extern "C" fn trampoline() {
extern "C" {
#[link_name = #name_handler]
static HANDLER: ::core::sync::atomic::AtomicPtr<u32>;
}
let p = HANDLER.load(::core::sync::atomic::Ordering::Acquire);
if !p.is_null() {
let f: fn() = ::core::mem::transmute(p);
f()
}
}
static TAKEN: ::core::sync::atomic::AtomicBool = ::core::sync::atomic::AtomicBool::new(false);
if TAKEN.compare_and_swap(false, true, ::core::sync::atomic::Ordering::AcqRel) {
panic!("IRQ Already taken");
}
let irq: interrupt::#name_interrupt = unsafe { ::core::mem::transmute(()) };
irq
}
};
result.into()
}

50
embassy-nrf/src/buffered_uarte.rs
View File

@ -17,10 +17,10 @@ use embedded_hal::digital::v2::OutputPin;
use crate::hal::gpio::{Floating, Input, Output, Pin as GpioPin, Port as GpioPort, PushPull};
use crate::interrupt;
use crate::interrupt::CriticalSection;
use crate::interrupt::{CriticalSection, OwnedInterrupt};
#[cfg(any(feature = "52833", feature = "52840", feature = "9160"))]
use crate::pac::UARTE1;
use crate::pac::{uarte0, Interrupt, UARTE0};
use crate::pac::{uarte0, UARTE0};
// Re-export SVD variants to allow user to directly set values
pub use uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Parity};
@ -141,8 +141,9 @@ pub struct BufferedUarte<T: Instance> {
// public because it needs to be used in Instance::{get_state, set_state}, but
// should not be used outside the module
#[doc(hidden)]
pub struct UarteState<T> {
pub struct UarteState<T: Instance> {
inner: T,
irq: T::Interrupt,
rx: RingBuf,
rx_state: RxState,
@ -164,7 +165,13 @@ fn port_bit(port: GpioPort) -> bool {
}
impl<T: Instance> BufferedUarte<T> {
pub fn new(uarte: T, mut pins: Pins, parity: Parity, baudrate: Baudrate) -> Self {
pub fn new(
uarte: T,
irq: T::Interrupt,
mut pins: Pins,
parity: Parity,
baudrate: Baudrate,
) -> Self {
// Select pins
uarte.psel.rxd.write(|w| {
let w = unsafe { w.pin().bits(pins.rxd.pin()) };
@ -222,6 +229,7 @@ impl<T: Instance> BufferedUarte<T> {
started: false,
state: UnsafeCell::new(UarteState {
inner: uarte,
irq,
rx: RingBuf::new(),
rx_state: RxState::Idle,
@ -287,9 +295,12 @@ impl<T: Instance> AsyncWrite for BufferedUarte<T> {
impl<T: Instance> UarteState<T> {
pub fn start(self: Pin<&mut Self>) {
interrupt::set_priority(T::interrupt(), interrupt::Priority::Level7);
interrupt::enable(T::interrupt());
interrupt::pend(T::interrupt());
self.irq.set_handler(|| unsafe {
interrupt::free(|cs| T::get_state(cs).as_mut().unwrap().on_interrupt());
});
self.irq.pend();
self.irq.enable();
}
fn poll_fill_buf(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Result<&[u8]>> {
@ -324,7 +335,7 @@ impl<T: Instance> UarteState<T> {
let this = unsafe { self.get_unchecked_mut() };
trace!("consume {:?}", amt);
this.rx.pop(amt);
interrupt::pend(T::interrupt());
this.irq.pend();
}
fn poll_write(self: Pin<&mut Self>, cx: &mut Context<'_>, buf: &[u8]) -> Poll<Result<usize>> {
@ -350,7 +361,7 @@ impl<T: Instance> UarteState<T> {
// before any DMA action has started
compiler_fence(Ordering::SeqCst);
interrupt::pend(T::interrupt());
this.irq.pend();
Poll::Ready(Ok(n))
}
@ -509,7 +520,7 @@ mod private {
}
pub trait Instance: Deref<Target = uarte0::RegisterBlock> + Sized + private::Sealed {
fn interrupt() -> Interrupt;
type Interrupt: OwnedInterrupt;
#[doc(hidden)]
fn get_state(_cs: &CriticalSection) -> *mut UarteState<Self>;
@ -518,25 +529,12 @@ pub trait Instance: Deref<Target = uarte0::RegisterBlock> + Sized + private::Sea
fn set_state(_cs: &CriticalSection, state: *mut UarteState<Self>);
}
#[interrupt]
unsafe fn UARTE0_UART0() {
interrupt::free(|cs| UARTE0::get_state(cs).as_mut().unwrap().on_interrupt());
}
#[cfg(any(feature = "52833", feature = "52840", feature = "9160"))]
#[interrupt]
unsafe fn UARTE1() {
interrupt::free(|cs| UARTE1::get_state(cs).as_mut().unwrap().on_interrupt());
}
static mut UARTE0_STATE: *mut UarteState<UARTE0> = ptr::null_mut();
#[cfg(any(feature = "52833", feature = "52840", feature = "9160"))]
static mut UARTE1_STATE: *mut UarteState<UARTE1> = ptr::null_mut();
impl Instance for UARTE0 {
fn interrupt() -> Interrupt {
Interrupt::UARTE0_UART0
}
type Interrupt = interrupt::UARTE0_UART0Interrupt;
fn get_state(_cs: &CriticalSection) -> *mut UarteState<Self> {
unsafe { UARTE0_STATE } // Safe because of CriticalSection
@ -548,9 +546,7 @@ impl Instance for UARTE0 {
#[cfg(any(feature = "52833", feature = "52840", feature = "9160"))]
impl Instance for UARTE1 {
fn interrupt() -> Interrupt {
Interrupt::UARTE1
}
type Interrupt = interrupt::UARTE1Interrupt;
fn get_state(_cs: &CriticalSection) -> *mut UarteState<Self> {
unsafe { UARTE1_STATE } // Safe because of CriticalSection

75
embassy-nrf/src/gpiote.rs
View File

@ -7,6 +7,7 @@ use embassy::util::Signal;
use crate::hal::gpio::{Input, Level, Output, Pin, Port};
use crate::interrupt;
use crate::interrupt::OwnedInterrupt;
use crate::pac::generic::Reg;
use crate::pac::gpiote::_TASKS_OUT;
#[cfg(any(feature = "52833", feature = "52840"))]
@ -58,7 +59,7 @@ pub enum NewChannelError {
}
impl Gpiote {
pub fn new(gpiote: GPIOTE) -> Self {
pub fn new(gpiote: GPIOTE, irq: interrupt::GPIOTEInterrupt) -> Self {
#[cfg(any(feature = "52833", feature = "52840"))]
let ports = unsafe { &[&*P0::ptr(), &*P1::ptr()] };
#[cfg(not(any(feature = "52833", feature = "52840")))]
@ -74,8 +75,9 @@ impl Gpiote {
// Enable interrupts
gpiote.events_port.write(|w| w);
gpiote.intenset.write(|w| w.port().set());
interrupt::unpend(interrupt::GPIOTE);
interrupt::enable(interrupt::GPIOTE);
irq.set_handler(Self::on_irq);
irq.unpend();
irq.enable();
Self {
inner: gpiote,
@ -293,6 +295,39 @@ impl Gpiote {
})
})
}
unsafe fn on_irq() {
let s = &(*INSTANCE);
for i in 0..8 {
if s.inner.events_in[i].read().bits() != 0 {
s.inner.events_in[i].write(|w| w);
s.channel_signals[i].signal(());
}
}
if s.inner.events_port.read().bits() != 0 {
s.inner.events_port.write(|w| w);
#[cfg(any(feature = "52833", feature = "52840"))]
let ports = &[&*P0::ptr(), &*P1::ptr()];
#[cfg(not(any(feature = "52833", feature = "52840")))]
let ports = &[&*P0::ptr()];
let mut work = true;
while work {
work = false;
for (port, &p) in ports.iter().enumerate() {
for pin in BitIter(p.latch.read().bits()) {
work = true;
p.pin_cnf[pin as usize].modify(|_, w| w.sense().disabled());
p.latch.write(|w| w.bits(1 << pin));
s.port_signals[port * 32 + pin as usize].signal(());
}
}
}
}
}
}
pub struct PortInputFuture<'a, T> {
@ -413,40 +448,6 @@ impl<'a> OutputChannel<'a> {
}
}
#[interrupt]
unsafe fn GPIOTE() {
let s = &(*INSTANCE);
for i in 0..8 {
if s.inner.events_in[i].read().bits() != 0 {
s.inner.events_in[i].write(|w| w);
s.channel_signals[i].signal(());
}
}
if s.inner.events_port.read().bits() != 0 {
s.inner.events_port.write(|w| w);
#[cfg(any(feature = "52833", feature = "52840"))]
let ports = &[&*P0::ptr(), &*P1::ptr()];
#[cfg(not(any(feature = "52833", feature = "52840")))]
let ports = &[&*P0::ptr()];
let mut work = true;
while work {
work = false;
for (port, &p) in ports.iter().enumerate() {
for pin in BitIter(p.latch.read().bits()) {
work = true;
p.pin_cnf[pin as usize].modify(|_, w| w.sense().disabled());
p.latch.write(|w| w.bits(1 << pin));
s.port_signals[port * 32 + pin as usize].signal(());
}
}
}
}
}
struct BitIter(u32);
impl Iterator for BitIter {

250
embassy-nrf/src/interrupt.rs
View File

@ -5,12 +5,13 @@
use core::sync::atomic::{compiler_fence, Ordering};
use crate::pac::{NVIC, NVIC_PRIO_BITS};
use crate::pac::NVIC_PRIO_BITS;
// Re-exports
pub use crate::pac::Interrupt;
pub use crate::pac::Interrupt::*; // needed for cortex-m-rt #[interrupt]
pub use cortex_m::interrupt::{CriticalSection, Mutex};
pub use embassy::interrupt::{declare, take, OwnedInterrupt};
#[derive(Debug, Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
@ -26,14 +27,8 @@ pub enum Priority {
Level7 = 7,
}
impl Priority {
#[inline]
fn to_nvic(self) -> u8 {
(self as u8) << (8 - NVIC_PRIO_BITS)
}
#[inline]
fn from_nvic(priority: u8) -> Self {
impl From<u8> for Priority {
fn from(priority: u8) -> Self {
match priority >> (8 - NVIC_PRIO_BITS) {
0 => Self::Level0,
1 => Self::Level1,
@ -48,6 +43,12 @@ impl Priority {
}
}
impl From<Priority> for u8 {
fn from(p: Priority) -> Self {
(p as u8) << (8 - NVIC_PRIO_BITS)
}
}
#[inline]
pub fn free<F, R>(f: F) -> R
where
@ -77,53 +78,204 @@ where
}
}
#[inline]
pub fn enable(irq: Interrupt) {
unsafe {
NVIC::unmask(irq);
}
#[cfg(feature = "52810")]
mod irqs {
use super::*;
declare!(POWER_CLOCK);
declare!(RADIO);
declare!(UARTE0_UART0);
declare!(TWIM0_TWIS0_TWI0);
declare!(SPIM0_SPIS0_SPI0);
declare!(GPIOTE);
declare!(SAADC);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(TEMP);
declare!(RNG);
declare!(ECB);
declare!(CCM_AAR);
declare!(WDT);
declare!(RTC1);
declare!(QDEC);
declare!(COMP);
declare!(SWI0_EGU0);
declare!(SWI1_EGU1);
declare!(SWI2);
declare!(SWI3);
declare!(SWI4);
declare!(SWI5);
declare!(PWM0);
declare!(PDM);
}
#[inline]
pub fn disable(irq: Interrupt) {
NVIC::mask(irq);
#[cfg(feature = "52811")]
mod irqs {
use super::*;
declare!(POWER_CLOCK);
declare!(RADIO);
declare!(UARTE0_UART0);
declare!(TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1);
declare!(SPIM0_SPIS0_SPI0);
declare!(GPIOTE);
declare!(SAADC);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(TEMP);
declare!(RNG);
declare!(ECB);
declare!(CCM_AAR);
declare!(WDT);
declare!(RTC1);
declare!(QDEC);
declare!(COMP);
declare!(SWI0_EGU0);
declare!(SWI1_EGU1);
declare!(SWI2);
declare!(SWI3);
declare!(SWI4);
declare!(SWI5);
declare!(PWM0);
declare!(PDM);
}
#[inline]
pub fn is_active(irq: Interrupt) -> bool {
NVIC::is_active(irq)
#[cfg(feature = "52832")]
mod irqs {
use super::*;
declare!(POWER_CLOCK);
declare!(RADIO);
declare!(UARTE0_UART0);
declare!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
declare!(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
declare!(NFCT);
declare!(GPIOTE);
declare!(SAADC);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(TEMP);
declare!(RNG);
declare!(ECB);
declare!(CCM_AAR);
declare!(WDT);
declare!(RTC1);
declare!(QDEC);
declare!(COMP_LPCOMP);
declare!(SWI0_EGU0);
declare!(SWI1_EGU1);
declare!(SWI2_EGU2);
declare!(SWI3_EGU3);
declare!(SWI4_EGU4);
declare!(SWI5_EGU5);
declare!(TIMER3);
declare!(TIMER4);
declare!(PWM0);
declare!(PDM);
declare!(MWU);
declare!(PWM1);
declare!(PWM2);
declare!(SPIM2_SPIS2_SPI2);
declare!(RTC2);
declare!(I2S);
declare!(FPU);
}
#[inline]
pub fn is_enabled(irq: Interrupt) -> bool {
NVIC::is_enabled(irq)
#[cfg(feature = "52833")]
mod irqs {
use super::*;
declare!(POWER_CLOCK);
declare!(RADIO);
declare!(UARTE0_UART0);
declare!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
declare!(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
declare!(NFCT);
declare!(GPIOTE);
declare!(SAADC);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(TEMP);
declare!(RNG);
declare!(ECB);
declare!(CCM_AAR);
declare!(WDT);
declare!(RTC1);
declare!(QDEC);
declare!(COMP_LPCOMP);
declare!(SWI0_EGU0);
declare!(SWI1_EGU1);
declare!(SWI2_EGU2);
declare!(SWI3_EGU3);
declare!(SWI4_EGU4);
declare!(SWI5_EGU5);
declare!(TIMER3);
declare!(TIMER4);
declare!(PWM0);
declare!(PDM);
declare!(MWU);
declare!(PWM1);
declare!(PWM2);
declare!(SPIM2_SPIS2_SPI2);
declare!(RTC2);
declare!(I2S);
declare!(FPU);
declare!(USBD);
declare!(UARTE1);
declare!(PWM3);
declare!(SPIM3);
}
#[inline]
pub fn is_pending(irq: Interrupt) -> bool {
NVIC::is_pending(irq)
#[cfg(feature = "52840")]
mod irqs {
use super::*;
declare!(POWER_CLOCK);
declare!(RADIO);
declare!(UARTE0_UART0);
declare!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
declare!(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
declare!(NFCT);
declare!(GPIOTE);
declare!(SAADC);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(TEMP);
declare!(RNG);
declare!(ECB);
declare!(CCM_AAR);
declare!(WDT);
declare!(RTC1);
declare!(QDEC);
declare!(COMP_LPCOMP);
declare!(SWI0_EGU0);
declare!(SWI1_EGU1);
declare!(SWI2_EGU2);
declare!(SWI3_EGU3);
declare!(SWI4_EGU4);
declare!(SWI5_EGU5);
declare!(TIMER3);
declare!(TIMER4);
declare!(PWM0);
declare!(PDM);
declare!(MWU);
declare!(PWM1);
declare!(PWM2);
declare!(SPIM2_SPIS2_SPI2);
declare!(RTC2);
declare!(I2S);
declare!(FPU);
declare!(USBD);
declare!(UARTE1);
declare!(QSPI);
declare!(CRYPTOCELL);
declare!(PWM3);
declare!(SPIM3);
}
#[inline]
pub fn pend(irq: Interrupt) {
NVIC::pend(irq)
}
#[inline]
pub fn unpend(irq: Interrupt) {
NVIC::unpend(irq)
}
#[inline]
pub fn get_priority(irq: Interrupt) -> Priority {
Priority::from_nvic(NVIC::get_priority(irq))
}
#[inline]
pub fn set_priority(irq: Interrupt, prio: Priority) {
unsafe {
cortex_m::peripheral::Peripherals::steal()
.NVIC
.set_priority(irq, prio.to_nvic())
}
}
pub use irqs::*;

15
embassy-nrf/src/qspi.rs
View File

@ -2,6 +2,7 @@ use crate::fmt::{assert, assert_eq, panic, *};
use core::future::Future;
use crate::hal::gpio::{Output, Pin as GpioPin, Port as GpioPort, PushPull};
use crate::interrupt::{OwnedInterrupt, QSPIInterrupt};
use crate::pac::{Interrupt, QSPI};
pub use crate::pac::qspi::ifconfig0::ADDRMODE_A as AddressMode;
@ -22,8 +23,6 @@ pub use crate::pac::qspi::ifconfig0::WRITEOC_A as WriteOpcode;
use embassy::flash::{Error, Flash};
use embassy::util::{DropBomb, Signal};
use crate::interrupt;
pub struct Pins {
pub sck: GpioPin<Output<PushPull>>,
pub csn: GpioPin<Output<PushPull>>,
@ -59,7 +58,7 @@ fn port_bit(port: GpioPort) -> bool {
}
impl Qspi {
pub fn new(qspi: QSPI, config: Config) -> Self {
pub fn new(qspi: QSPI, irq: QSPIInterrupt, config: Config) -> Self {
qspi.psel.sck.write(|w| {
let pin = &config.pins.sck;
let w = unsafe { w.pin().bits(pin.pin()) };
@ -146,9 +145,10 @@ impl Qspi {
// Enable READY interrupt
SIGNAL.reset();
qspi.intenset.write(|w| w.ready().set());
interrupt::set_priority(Interrupt::QSPI, interrupt::Priority::Level7);
interrupt::unpend(Interrupt::QSPI);
interrupt::enable(Interrupt::QSPI);
irq.set_handler(irq_handler);
irq.unpend();
irq.enable();
Self { inner: qspi }
}
@ -347,8 +347,7 @@ impl Flash for Qspi {
static SIGNAL: Signal<()> = Signal::new();
#[interrupt]
unsafe fn QSPI() {
unsafe fn irq_handler() {
let p = crate::pac::Peripherals::steal().QSPI;
if p.events_ready.read().events_ready().bit_is_set() {
p.events_ready.reset();

36
embassy-nrf/src/rtc.rs
View File

@ -2,10 +2,10 @@ use core::cell::Cell;
use core::ops::Deref;
use core::sync::atomic::{AtomicU32, Ordering};
use embassy::time::Clock;
use embassy::time::{Clock, Instant};
use crate::interrupt;
use crate::interrupt::{CriticalSection, Mutex};
use crate::interrupt::{CriticalSection, Mutex, OwnedInterrupt};
use crate::pac::{rtc0, Interrupt, RTC0, RTC1};
#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
@ -56,8 +56,9 @@ impl AlarmState {
const ALARM_COUNT: usize = 3;
pub struct RTC<T> {
pub struct RTC<T: Instance> {
rtc: T,
irq: T::Interrupt,
/// Number of 2^23 periods elapsed since boot.
///
@ -75,13 +76,14 @@ pub struct RTC<T> {
alarms: Mutex<[AlarmState; ALARM_COUNT]>,
}
unsafe impl<T> Send for RTC<T> {}
unsafe impl<T> Sync for RTC<T> {}
unsafe impl<T: Instance> Send for RTC<T> {}
unsafe impl<T: Instance> Sync for RTC<T> {}
impl<T: Instance> RTC<T> {
pub fn new(rtc: T) -> Self {
pub fn new(rtc: T, irq: T::Interrupt) -> Self {
Self {
rtc,
irq,
period: AtomicU32::new(0),
alarms: Mutex::new([AlarmState::new(), AlarmState::new(), AlarmState::new()]),
}
@ -103,7 +105,10 @@ impl<T: Instance> RTC<T> {
while self.rtc.counter.read().bits() != 0 {}
T::set_rtc_instance(self);
interrupt::enable(T::INTERRUPT);
self.irq
.set_handler(|| T::get_rtc_instance().on_interrupt());
self.irq.unpend();
self.irq.enable();
}
fn on_interrupt(&self) {
@ -234,18 +239,18 @@ impl<T: Instance> embassy::time::Alarm for Alarm<T> {
/// Implemented by all RTC instances.
pub trait Instance: Deref<Target = rtc0::RegisterBlock> + Sized + 'static {
/// The interrupt associated with this RTC instance.
const INTERRUPT: Interrupt;
type Interrupt: OwnedInterrupt;
fn set_rtc_instance(rtc: &'static RTC<Self>);
fn get_rtc_instance() -> &'static RTC<Self>;
}
macro_rules! impl_instance {
($name:ident, $static_name:ident) => {
($name:ident, $irq_name:path, $static_name:ident) => {
static mut $static_name: Option<&'static RTC<$name>> = None;
impl Instance for $name {
const INTERRUPT: Interrupt = Interrupt::$name;
type Interrupt = $irq_name;
fn set_rtc_instance(rtc: &'static RTC<Self>) {
unsafe { $static_name = Some(rtc) }
}
@ -253,16 +258,11 @@ macro_rules! impl_instance {
unsafe { $static_name.unwrap() }
}
}
#[interrupt]
fn $name() {
$name::get_rtc_instance().on_interrupt();
}
};
}
impl_instance!(RTC0, RTC0_INSTANCE);
impl_instance!(RTC1, RTC1_INSTANCE);
impl_instance!(RTC0, interrupt::RTC0Interrupt, RTC0_INSTANCE);
impl_instance!(RTC1, interrupt::RTC1Interrupt, RTC1_INSTANCE);
#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
impl_instance!(RTC2, RTC2_INSTANCE);
impl_instance!(RTC2, interrupt::RTC2Interrupt, RTC2_INSTANCE);

76
embassy/src/interrupt.rs Normal file
View File

@ -0,0 +1,76 @@
use core::mem;
use core::ptr;
use core::sync::atomic::{AtomicBool, AtomicPtr, Ordering};
use cortex_m::peripheral::NVIC;
pub use embassy_macros::interrupt_declare as declare;
pub use embassy_macros::interrupt_take as take;
struct NrWrap(u8);
unsafe impl cortex_m::interrupt::Nr for NrWrap {
fn nr(&self) -> u8 {
self.0
}
}
pub unsafe trait OwnedInterrupt {
type Priority: From<u8> + Into<u8> + Copy;
fn number(&self) -> u8;
#[doc(hidden)]
unsafe fn __handler(&self) -> &'static AtomicPtr<u32>;
fn set_handler(&self, handler: unsafe fn()) {
unsafe { self.__handler() }.store(handler as *mut u32, Ordering::Release);
}
#[inline]
fn enable(&self) {
unsafe {
NVIC::unmask(NrWrap(self.number()));
}
}
#[inline]
fn disable(&self) {
NVIC::mask(NrWrap(self.number()));
}
#[inline]
fn is_active(&self) -> bool {
NVIC::is_active(NrWrap(self.number()))
}
#[inline]
fn is_enabled(&self) -> bool {
NVIC::is_enabled(NrWrap(self.number()))
}
#[inline]
fn is_pending(&self) -> bool {
NVIC::is_pending(NrWrap(self.number()))
}
#[inline]
fn pend(&self) {
NVIC::pend(NrWrap(self.number()))
}
#[inline]
fn unpend(&self) {
NVIC::unpend(NrWrap(self.number()))
}
#[inline]
fn get_priority(&self) -> Self::Priority {
Self::Priority::from(NVIC::get_priority(NrWrap(self.number())))
}
#[inline]
fn set_priority(&self, prio: Self::Priority) {
unsafe {
cortex_m::peripheral::Peripherals::steal()
.NVIC
.set_priority(NrWrap(self.number()), prio.into())
}
}
}

1
embassy/src/lib.rs
View File

@ -9,6 +9,7 @@ pub(crate) mod fmt;
pub mod executor;
pub mod flash;
pub mod interrupt;
pub mod io;
pub mod rand;
pub mod time;

4
examples/src/bin/gpiote.rs
View File

@ -7,18 +7,20 @@ mod example_common;
use example_common::*;
use cortex_m_rt::entry;
use defmt::panic;
use nrf52840_hal::gpio;
use embassy::executor::{task, Executor};
use embassy::util::Forever;
use embassy_nrf::gpiote;
use embassy_nrf::interrupt;
#[task]
async fn run() {
let p = unwrap!(embassy_nrf::pac::Peripherals::take());
let port0 = gpio::p0::Parts::new(p.P0);
let g = gpiote::Gpiote::new(p.GPIOTE);
let g = gpiote::Gpiote::new(p.GPIOTE, interrupt::take!(GPIOTE));
info!("Starting!");

4
examples/src/bin/gpiote_port.rs
View File

@ -8,11 +8,13 @@ use example_common::*;
use core::mem;
use cortex_m_rt::entry;
use defmt::panic;
use nrf52840_hal::gpio;
use embassy::executor::{task, Executor};
use embassy::util::Forever;
use embassy_nrf::gpiote::{Gpiote, PortInputPolarity};
use embassy_nrf::interrupt;
async fn button(g: &Gpiote, n: usize, pin: gpio::Pin<gpio::Input<gpio::PullUp>>) {
loop {
@ -28,7 +30,7 @@ async fn run() {
let p = unwrap!(embassy_nrf::pac::Peripherals::take());
let port0 = gpio::p0::Parts::new(p.P0);
let g = Gpiote::new(p.GPIOTE);
let g = Gpiote::new(p.GPIOTE, interrupt::take!(GPIOTE));
info!(
"sizeof Signal<()> = {:usize}",
mem::size_of::<embassy::util::Signal<()>>()

19
examples/src/bin/multiprio.rs
View File

@ -61,7 +61,9 @@
mod example_common;
use example_common::*;
use cortex_m::peripheral::NVIC;
use cortex_m_rt::entry;
use defmt::panic;
use nrf52840_hal::clocks;
use embassy::executor::{task, Executor};
@ -130,7 +132,7 @@ fn main() -> ! {
.set_lfclk_src_external(clocks::LfOscConfiguration::NoExternalNoBypass)
.start_lfclk();
let rtc = RTC.put(rtc::RTC::new(p.RTC1));
let rtc = RTC.put(rtc::RTC::new(p.RTC1, interrupt::take!(RTC1)));
rtc.start();
unsafe { embassy::time::set_clock(rtc) };
@ -138,17 +140,20 @@ fn main() -> ! {
let executor_low = EXECUTOR_LOW.put(Executor::new_with_alarm(alarm_low, cortex_m::asm::sev));
let alarm_med = ALARM_MED.put(rtc.alarm1());
let executor_med = EXECUTOR_MED.put(Executor::new_with_alarm(alarm_med, || {
interrupt::pend(interrupt::SWI0_EGU0)
NVIC::pend(interrupt::SWI0_EGU0)
}));
let alarm_high = ALARM_HIGH.put(rtc.alarm2());
let executor_high = EXECUTOR_HIGH.put(Executor::new_with_alarm(alarm_high, || {
interrupt::pend(interrupt::SWI1_EGU1)
NVIC::pend(interrupt::SWI1_EGU1)
}));
interrupt::set_priority(interrupt::SWI0_EGU0, interrupt::Priority::Level7);
interrupt::set_priority(interrupt::SWI1_EGU1, interrupt::Priority::Level6);
interrupt::enable(interrupt::SWI0_EGU0);
interrupt::enable(interrupt::SWI1_EGU1);
unsafe {
let mut nvic: NVIC = core::mem::transmute(());
nvic.set_priority(interrupt::SWI0_EGU0, 7 << 5);
nvic.set_priority(interrupt::SWI1_EGU1, 6 << 5);
NVIC::unmask(interrupt::SWI0_EGU0);
NVIC::unmask(interrupt::SWI1_EGU1);
}
unwrap!(executor_low.spawn(run_low()));
unwrap!(executor_med.spawn(run_med()));

5
examples/src/bin/qspi.rs
View File

@ -13,7 +13,7 @@ use nrf52840_hal::gpio;
use embassy::executor::{task, Executor};
use embassy::flash::Flash;
use embassy::util::Forever;
use embassy_nrf::qspi;
use embassy_nrf::{interrupt, qspi};
const PAGE_SIZE: usize = 4096;
@ -68,7 +68,8 @@ async fn run() {
deep_power_down: None,
};
let mut q = qspi::Qspi::new(p.QSPI, config);
let irq = interrupt::take!(QSPI);
let mut q = qspi::Qspi::new(p.QSPI, irq, config);
let mut id = [1; 3];
q.custom_instruction(0x9F, &[], &mut id).await.unwrap();

8
examples/src/bin/rtc_async.rs
View File

@ -8,13 +8,13 @@ use example_common::*;
use core::mem::MaybeUninit;
use cortex_m_rt::entry;
use nrf52840_hal::clocks;
use defmt::panic;
use embassy::executor::{task, Executor};
use embassy::time::{Clock, Duration, Timer};
use embassy::util::Forever;
use embassy_nrf::pac;
use embassy_nrf::rtc;
use embassy_nrf::{interrupt, rtc};
use nrf52840_hal::clocks;
#[task]
async fn run1() {
@ -47,7 +47,7 @@ fn main() -> ! {
.set_lfclk_src_external(clocks::LfOscConfiguration::NoExternalNoBypass)
.start_lfclk();
let rtc = RTC.put(rtc::RTC::new(p.RTC1));
let rtc = RTC.put(rtc::RTC::new(p.RTC1, interrupt::take!(RTC1)));
rtc.start();
unsafe { embassy::time::set_clock(rtc) };

7
examples/src/bin/rtc_raw.rs
View File

@ -8,8 +8,9 @@ use example_common::*;
use core::mem::MaybeUninit;
use cortex_m_rt::entry;
use defmt::panic;
use embassy::time::{Alarm, Clock};
use embassy_nrf::rtc;
use embassy_nrf::{interrupt, rtc};
use nrf52840_hal::clocks;
static mut RTC: MaybeUninit<rtc::RTC<embassy_nrf::pac::RTC1>> = MaybeUninit::uninit();
@ -25,9 +26,11 @@ fn main() -> ! {
.set_lfclk_src_external(clocks::LfOscConfiguration::NoExternalNoBypass)
.start_lfclk();
let irq = interrupt::take!(RTC1);
let rtc: &'static _ = unsafe {
let ptr = RTC.as_mut_ptr();
ptr.write(rtc::RTC::new(p.RTC1));
ptr.write(rtc::RTC::new(p.RTC1, irq));
&*ptr
};

4
examples/src/bin/uart.rs
View File

@ -7,6 +7,7 @@ mod example_common;
use example_common::*;
use cortex_m_rt::entry;
use defmt::panic;
use futures::pin_mut;
use nrf52840_hal::gpio;
@ -14,6 +15,7 @@ use embassy::executor::{task, Executor};
use embassy::io::{AsyncBufRead, AsyncBufReadExt, AsyncWrite, AsyncWriteExt};
use embassy::util::Forever;
use embassy_nrf::buffered_uarte;
use embassy_nrf::interrupt;
#[task]
async fn run() {
@ -31,8 +33,10 @@ async fn run() {
rts: None,
};
let irq = interrupt::take!(UARTE0_UART0);
let u = buffered_uarte::BufferedUarte::new(
p.UARTE0,
irq,
pins,
buffered_uarte::Parity::EXCLUDED,
buffered_uarte::Baudrate::BAUD115200,