stm32: move dbgmcu stuff to toplevel config setting, defaulting to true.
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@ -68,12 +68,14 @@ pub use generated::{peripherals, Peripherals};
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#[non_exhaustive]
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pub struct Config {
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pub rcc: rcc::Config,
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pub enable_debug_during_sleep: bool,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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rcc: Default::default(),
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enable_debug_during_sleep: true,
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}
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}
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}
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@ -83,6 +85,10 @@ pub fn init(config: Config) -> Peripherals {
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let p = Peripherals::take();
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unsafe {
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if config.enable_debug_during_sleep {
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dbgmcu::Dbgmcu::enable_all();
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}
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gpio::init();
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dma::init();
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#[cfg(exti)]
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@ -2,7 +2,6 @@ use core::marker::PhantomData;
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use embassy::util::Unborrow;
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use crate::dbgmcu::Dbgmcu;
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use crate::pac::{FLASH, RCC};
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use crate::peripherals;
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use crate::time::Hertz;
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@ -27,7 +26,6 @@ pub struct Config {
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pub sys_ck: Option<Hertz>,
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pub hclk: Option<Hertz>,
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pub pclk: Option<Hertz>,
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pub enable_debug_wfe: bool,
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}
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pub struct Rcc<'d> {
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@ -190,12 +188,6 @@ impl<'d> Rcc<'d> {
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}
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})
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}
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if self.config.enable_debug_wfe {
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RCC.ahbenr().modify(|w| w.set_dmaen(true));
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critical_section::with(|_| Dbgmcu::enable_all());
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}
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}
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Clocks {
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@ -21,7 +21,6 @@ pub struct Config {
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pub hclk: Option<Hertz>,
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pub pclk1: Option<Hertz>,
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pub pclk2: Option<Hertz>,
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pub enable_debug_wfe: bool,
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}
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/// RCC peripheral
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@ -176,15 +175,6 @@ impl<'d> Rcc<'d> {
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});
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}
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if self.config.enable_debug_wfe {
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unsafe {
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RCC.ahb1enr().modify(|w| w.set_dma1en(true));
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critical_section::with(|_| {
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crate::dbgmcu::Dbgmcu::enable_all();
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});
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}
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}
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Clocks {
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sys: Hertz(sysclk),
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apb1: Hertz(pclk1),
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@ -3,7 +3,7 @@ use core::marker::PhantomData;
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use embassy::util::Unborrow;
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use crate::pac::rcc::vals::Timpre;
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use crate::pac::{DBGMCU, RCC, SYSCFG};
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use crate::pac::{RCC, SYSCFG};
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use crate::peripherals;
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use crate::pwr::{Power, VoltageScale};
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use crate::rcc::{set_freqs, Clocks};
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@ -363,25 +363,6 @@ impl<'d> Rcc<'d> {
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}
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}
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/// Enables debugging during WFI/WFE
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///
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/// Set `enable_dma1` to true if you do not have at least one bus master (other than the CPU)
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/// enable during WFI/WFE
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pub fn enable_debug_wfe(&mut self, _dbg: &mut peripherals::DBGMCU, enable_dma1: bool) {
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// NOTE(unsafe) We have exclusive access to the RCC and DBGMCU
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unsafe {
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if enable_dma1 {
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RCC.ahb1enr().modify(|w| w.set_dma1en(true));
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}
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DBGMCU.cr().modify(|w| {
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w.set_dbgsleep_d1(true);
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w.set_dbgstby_d1(true);
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w.set_dbgstop_d1(true);
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});
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}
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}
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/// Setup traceclk
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/// Returns a pll1_r_ck
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fn traceclk_setup(&mut self, sys_use_pll1_p: bool) {
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@ -1,5 +1,4 @@
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pub use super::types::*;
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use crate::dbgmcu::Dbgmcu;
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use crate::pac;
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use crate::peripherals::{self, CRS, RCC, SYSCFG};
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use crate::rcc::{get_freqs, set_freqs, Clocks};
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@ -168,15 +167,6 @@ impl<'d> Rcc<'d> {
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unsafe { get_freqs() }
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}
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pub fn enable_debug_wfe(&mut self, _dbg: &mut peripherals::DBGMCU, enable_dma: bool) {
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// NOTE(unsafe) We have exclusive access to the RCC and DBGMCU
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unsafe {
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pac::RCC.ahbenr().modify(|w| w.set_dma1en(enable_dma));
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Dbgmcu::enable_all();
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}
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}
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pub fn enable_hsi48(&mut self, _syscfg: &mut SYSCFG, _crs: CRS) -> HSI48 {
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let rcc = pac::RCC;
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unsafe {
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