From 2cc9fea6d3720e21a856d83358f6fbc1da2aec8c Mon Sep 17 00:00:00 2001 From: Oliver Rockstedt Date: Fri, 15 Dec 2023 11:42:58 +0100 Subject: [PATCH] STM32H7: Allow PLL1 DIVP of 1 for certain series --- embassy-stm32/src/rcc/h.rs | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs index 1889eb28..18dff9f2 100644 --- a/embassy-stm32/src/rcc/h.rs +++ b/embassy-stm32/src/rcc/h.rs @@ -70,7 +70,9 @@ pub struct Pll { pub mul: PllMul, /// PLL P division factor. If None, PLL P output is disabled. - /// On PLL1, it must be even (in particular, it cannot be 1.) + /// On PLL1, it must be even for most series (in particular, + /// it cannot be 1 in series other than STM32H723/733, + /// STM32H725/735 and STM32H730.) pub divp: Option, /// PLL Q division factor. If None, PLL Q output is disabled. pub divq: Option, @@ -729,9 +731,12 @@ fn init_pll(num: usize, config: Option, input: &PllInput) -> PllOutput { let p = config.divp.map(|div| { if num == 0 { - // on PLL1, DIVP must be even. + // on PLL1, DIVP must be even for most series. // The enum value is 1 less than the divider, so check it's odd. + #[cfg(not(pwr_h7rm0468))] assert!(div.to_bits() % 2 == 1); + #[cfg(pwr_h7rm0468)] + assert!(div.to_bits() % 2 == 1 || div.to_bits() == 0); } vco_clk / div